MicroSQUID Force microscopy in a dilution refrigerator

We present a new generation of a scanning MicroSQUID microscope operating in an inverted dilution refrigerator. The MicroSQUIDs have a size of 1.21$ \ \mum\textsuperscript{2} and a magnetic flux sensitivity of 120 \mu\Phi_{0} / \sqrt{\textrm{Hz}}$and thus a field sensitivity of$550^{-6} \ \Phi_{0} / \sqrt{\textrm{Hz}}$550$ \ \mu \textrm{G}/ \sqrt{\textrm{Hz}}$. The scan range at low temperatures is about 80$\mu$m and a coarse displacement of 5 mm in x and y direction has been implemented. The MicroSQUID-to-sample distance is regulated using a tuning fork based force detection. A MicroSQUID-to-sample distance of 420 nm has been obtained. The reliable knowledge of this distance is necessary to obtain a trustworthy estimate of the absolute value of the superconducting penetration depth. An outlook will be given on the ongoing direction of development

Micro-manufacturing : research, technology outcomes and development issues

Besides continuing effort in developing MEMS-based manufacturing techniques, latest effort in Micro-manufacturing is also in Non-MEMS-based manufacturing. Research and technological development (RTD) in this field is encouraged by the increased demand on micro-components as well as promised development in the scaling down of the traditional macro-manufacturing processes for micro-length-scale manufacturing. This paper highlights some EU funded research activities in micro/nano-manufacturing, and gives examples of the latest development in micro-manufacturing methods/techniques, process chains, hybrid-processes, manufacturing equipment and supporting technologies/device, etc., which is followed by a summary of the achievements of the EU MASMICRO project. Finally, concluding remarks are given, which raise several issues concerning further development in micro-manufacturing

DAMO: Deep Agile Mask Optimization for Full Chip Scale

Continuous scaling of the VLSI system leaves a great challenge on manufacturing and optical proximity correction (OPC) is widely applied in conventional design flow for manufacturability optimization. Traditional techniques conducted OPC by leveraging a lithography model and suffered from prohibitive computational overhead, and mostly focused on optimizing a single clip without addressing how to tackle the full chip. In this paper, we present DAMO, a high performance and scalable deep learning-enabled OPC system for full chip scale. It is an end-to-end mask optimization paradigm which contains a Deep Lithography Simulator (DLS) for lithography modeling and a Deep Mask Generator (DMG) for mask pattern generation. Moreover, a novel layout splitting algorithm customized for DAMO is proposed to handle the full chip OPC problem. Extensive experiments show that DAMO outperforms the state-of-the-art OPC solutions in both academia and industrial commercial toolkit

Integrated optical bimodal waveguide biosensors : principles and applications

Altres ajuts: the ICN2 is funded by the CERCA program/Generalitat de Catalunya.Integrated optical biosensors have become one of the most compelling technologies for the achievement of highly sensitive, multianalyte, portable and easy to use point-of-care (POC) devices with tremendous impact in healthcare and environmental protection, among other application fields. In this context, bimodal waveguide (BiMW) interferometers have emerged over the last years as a powerful biosensor technology providing the benefits of extreme sensitivity under a label-free scheme, reliability and robustness within a highly compact footprint that can be integrated and multiplexed in lab-on-a-chip (LOC) platforms. In this review, we provide an overview of the state-of-the-art about integrated optical BiMW biosensors from the theoretical fundamentals to their practical implementation. Furthermore, we explore recent advances such as novel designs, integration in specific LOC systems and its application in real biosensing scenarios. Final remarks and perspectives on the potential impact of these biosensor interferometric structures are also provided, as well as some limitations that must be addressed in next steps

Layout regularity metric as a fast indicator of process variations

Integrated circuits design faces increasing challenge as we scale down due to the increase of the effect of sensitivity to process variations. Systematic variations induced by different steps in the lithography process affect both parametric and functional yields of the designs. These variations are known, themselves, to be affected by layout topologies. Design for Manufacturability (DFM) aims at defining techniques that mitigate variations and improve yield. Layout regularity is one of the trending techniques suggested by DFM to mitigate process variations effect. There are several solutions to create regular designs, like restricted design rules and regular fabrics. These regular solutions raised the need for a regularity metric. Metrics in literature are insufficient for different reasons; either because they are qualitative or computationally intensive. Furthermore, there is no study relating either lithography or electrical variations to layout regularity. In this work, layout regularity is studied in details and a new geometrical-based layout regularity metric is derived. This metric is verified against lithographic simulations and shows good correlation. Calculation of the metric takes only few minutes on 1mm x 1mm design, which is considered fast compared to the time taken by simulations. This makes it a good candidate for pre-processing the layout data and selecting certain areas of interest for lithographic simulations for faster throughput. The layout regularity metric is also compared against a model that measures electrical variations due to systematic lithographic variations. The validity of using the regularity metric to flag circuits that have high variability using the developed electrical variations model is shown. The regularity metric results compared to the electrical variability model results show matching percentage that can reach 80%, which means that this metric can be used as a fast indicator of designs more susceptible to lithography and hence electrical variations