Ultra Small Antenna and Low Power Receiver for Smart Dust Wireless Sensor Networks

Wireless Sensor Networks have the potential for profound impact on our daily lives. Smart Dust Wireless Sensor Networks (SDWSNs) are emerging members of the Wireless Sensor Network family with strict requirements on communication node sizes (1 cubic centimeter) and power consumption (< 2mW during short on-states). In addition, the large number of communication nodes needed in SDWSN require highly integrated solutions. This dissertation develops new design techniques for low-volume antennas and low-power receivers for SDWSN applications. In addition, it devises an antenna and low noise amplifier co-design methodology to increase the level of design integration, reduce receiver noise, and reduce the development cycle. This dissertation first establishes stringent principles for designing SDWSN electrically small antennas (ESAs). Based on these principles, a new ESA, the F-Inverted Compact Antenna (FICA), is designed at 916MHz. This FICA has a significant advantage in that it uses a small-size ground plane. The volume of this FICA (including the ground plane) is only 7% of other state-of-the-art ESAs, while its efficiency (48.53%) and gain (-1.38dBi) are comparable to antennas of much larger dimensions. A physics-based circuit model is developed for this FICA to assist system level design at the earliest stage, including optimization of the antenna performance. An antenna and low noise amplifier (LNA) co-design method is proposed and proven to be valid to design low power LNAs with the very low noise figure of only 1.5dB. To reduce receiver power consumption, this dissertation proposes a novel LNA active device and an input/ouput passive matching network optimization method. With this method, a power efficient high voltage gain cascode LNA was designed in a 0.13um CMOS process with only low quality factor inductors. This LNA has a 3.6dB noise figure, voltage gain of 24dB, input third intercept point (IIP3) of 3dBm, and power consumption of 1.5mW at 1.0V supply voltage. Its figure of merit, using the typical definition, is twice that of the best in the literature. A full low power receiver is developed with a sensitivity of -58dBm, chip area of 1.1mm2, and power consumption of 2.85mW

Design of Power/Analog/Digital Systems Through Mixed-Level Simulations

In recent years the development of the applications in the field of telecommunications, data processing, control, renewable energy generation, consumer and automotive electronics determined the need for increasingly complex systems, also in shorter time to meet the growing market demand. The increasing complexity is mainly due to the mixed nature of these systems that must be developed to accommodate the new functionalities and to satisfy the more stringent performance requirements of the emerging applications. This means a more complex design and verification process. The key to managing the increased design complexity is a structured and integrated design methodology which allows the sharing of different circuit implementations that can be at transistor level and/or at a higher level (i.e.HDL languages).In order to expedite the mixed systems design process it is necessary to provide: an integrated design methodology; a suitable supporting tool able to manage the entire design process and design complexity and its successive verification.It is essential that the different system blocks (power, analog, digital), described at different level of abstraction, can be co-simulated in the same design context. This capability is referred to as mixed-level simulation.One of the objectives of this research is to design a mixed system application referred to the control of a coupled step-up dc-dc converter. This latter consists of a power stage designed at transistor-level, also including accurate power device models, and the analog controller implemented using VerilogA modules. Digital controllers are becoming very attractive in dc-dc converters for their programmability, ability to implement sophisticated control schemes, and ease of integration with other digital systems. Thus, in this dissertation it will be presented a detailed design of a Flash Analog-to-Digital Converter (ADC). The designed ADC provides medium-high resolution associated to high-speed performance. This makes it useful not only for the control application aforementioned but also for applications with huge requirements in terms of speed and signal bandwidth. The entire design flow of the overall system has been conducted in the Cadence Design Environment that also provides the ability to mixed-level simulations. Furthermore, the technology process used for the ADC design is the IHP BiCMOS 0.25 µm by using 50 GHz NPN HBT devices

Ultra-Low-Power Sensors and Receivers for IoT Applications

The combination of ultra-low power analog front-ends and CMOS-compatible transducers enable new applications, such as environmental monitors, household appliances, health trackers, etc. that are seamlessly integrated into our daily lives. Furthermore, wireless connectivity allows many of these sensors to operate both independently and collectively. These techniques collectively fulfil the recent surge of internet-of-things (IoT) applications that have the potential to fundamentally change daily life for millions of people.In this dissertation, the circuit and system design of wireless receivers and sensors is presented that explores the challenges of implementing long lifespan, high accuracy, and large coverage range IoT sensor networks. The first is a wake-up receiver (WuRX), which continuously monitors the RF environment to wake up a higher-power radio upon detection of a predetermined RF signature. This work both improves sensitivity and reduces power over prior art through a multi-faceted design featuring an impedance transformation network with large passive voltage gain, an active envelope detector with high input impedance to facilitate large passive voltage gain, a low-power precision comparator, and a low-leakage digital baseband correlator.Although pushing the prior WuRX performance boundary by orders of magnitude, the first work shows moderate sensitivity, inferior temperature robustness, and large area with external lumped components. Thus, the second work shows a miniaturized WuRX that is temperature-compensated, yet still consumes only nano-watt power and millimeter area while operating at 9 GHz. To further reduce the area, a global common-mode feedback is utilized across the envelope detector and baseband amplifier that eliminates the need for off-chip ac-coupling components. Multiple temperature-compensation techniques are proposed to maintain constant bandwidth of the signal path and constant clock frequency. Both WuRXs operate at 0.4 V supply, consume near-zero power and achieve ~-70 dBm sensitivity.Lastly, the first reported CMOS 2-in-1 relative humidity and temperature sensor is presented. A unified analog front-end interfaces on-chip transducers and converts the inputs into a frequency vis a high-linearity frequency-locked loop. An incomplete-settling switched-capacitor-based Wheatstone bridge is proposed to sense the inputs in a power-efficient fashion

ULTRA LOW POWER FSK RECEIVER AND RF ENERGY HARVESTER

This thesis focuses on low power receiver design and energy harvesting techniques as methods for intelligently managing energy usage and energy sources. The goal is to build an inexhaustibly powered communication system that can be widely applied, such as through wireless sensor networks (WSNs). Low power circuit design and smart power management are techniques that are often used to extend the lifetime of such mobile devices. Both methods are utilized here to optimize power usage and sources. RF energy is a promising ambient energy source that is widely available in urban areas and which we investigate in detail. A harvester circuit is modeled and analyzed in detail at low power input. Based on the circuit analysis, a design procedure is given for a narrowband energy harvester. The antenna and harvester co-design methodology improves RF to DC energy conversion efficiency. The strategy of co-design of the antenna and the harvester creates opportunities to optimize the system power conversion efficiency. Previous surveys have found that ambient RF energy is spread broadly over the frequency domain; however, here it is demonstrated that it is theoretically impossible to harvest RF energy over a wide frequency band if the ambient RF energy source(s) are weak, owing to the voltage requirements. It is found that most of the ambient RF energy lies in a series of narrow bands. Two different versions of harvesters have been designed, fabricated, and tested. The simulated and measured results demonstrate a dual-band energy harvester that obtains over 9% efficiency for two different bands (900MHz and 1800MHz) at an input power as low as -19dBm. The DC output voltage of this harvester is over 1V, which can be used to recharge the battery to form an inexhaustibly powered communication system. A new phase locked loop based receiver architecture is developed to avoid the significant conversion losses associated with OOK architectures. This also helps to minimize power consumption. A new low power mixer circuit has also been designed, and a detailed analysis is provided. Based on the mixer, a low power phase locked loop (PLL) based receiver has been designed, fabricated and measured. A power management circuit and a low power transceiver system have also been co-designed to provide a system on chip solution. The low power voltage regulator is designed to handle a variety of battery voltage, environmental temperature, and load conditions. The whole system can work with a battery and an application specific integrated circuit (ASIC) as a sensor node of a WSN network

A Fully Integrated CMOS Receiver.

The rapidly growing wireless communication market is creating an increasing demand for low-cost highly-integrated radio frequency (RF) communication systems. This dissertation focuses on techniques to enable fully-integrated, wireless receivers incorporating all passive components, including the antenna, and also incorporating baseband synchronization on-chip. Not only is the receiver small in size and requires very low power, but it also delivers synchronized demodulated data. This research targets applications such as implantable neuroprosthetic devices and environmental wireless sensors, which need short range, low data-rate wireless communications but a long lifetime. To achieve these goals, the super-regenerative architecture is used, since power consumption with this architecture is low due to the simplified receiver architecture. This dissertation presents a 5GHz single chip receiver incorporating a compact on-chip 5 GHz slot antenna (50 times smaller than traditional dipole antennas) and a digital received data synchronization. A compact capacitively-loaded 5 GHz standing-wave resonator is used to improve the energy efficiency. An all-digital PLL timing scheme synchronizes the received data clock. A new type of low-power envelope detector is incorporated to increase the data rate and efficiency. The receiver achieves a data rate up to 1.2 Mb/s, dissipates 6.6 mW from a 1.5 V supply. The novel on-chip capacitively-loaded, transmission-line-standing-wave resonator is employed instead of a conventional low-Q on-chip inductor. The simulated quality factor of the resonator is very high (35), and is verified by phase-noise measurements of a prototype 5GHz Voltage Control Oscillator (VCO) incorporating this resonator. The prototype VCO, implemented in 0.13 µm CMOS, dissipates 3 mW from a 1.2 V supply, and achieves a measured phase noise of -117 dBc/Hz at a 1 MHz offset. In the on-chip antenna an efficient shielding technique is used to shield the antenna from the low-resistivity substrate underneath. Two standalone on-chip slot antenna prototypes were designed and fabricated in 0.13 µm CMOS. The 9 GHz prototype occupies a die area of only 0.3 mm2, has an active gain of -4.4 dBi and an efficiency of 9%. The second prototype occupies a die area of 0.47 mm2, and achieves a passive gain of approximately -17.0 dBi at 5 GHz.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/60739/1/shid_1.pd

Low power rf transceivers

This thesis details the analysis and design of ultra-low power radio transceivers operating at microwave frequencies. Hybrid prototypes and Monolithic Microwave Integrated Circuits (MMICs) which achieve power consumptions of less than 1 mW and theoretical operating ranges of over 10 m are described. The motivation behind the design of circuits exhibiting ultra low power consumption and, in the case of the MMICs, small size is the emerging technology of Wireless Sensor Networks (WSN). WSNs consist of spatially distributed ‘nodes’ or ‘specks’ each with their own renewable energy source, one or more sensors, limited memory, processing capability and radio or optical link. The idea is that specks within a ‘speckzone’ cooperate and share computational resources to perform complex tasks such as monitoring fire hazards, radiation levels or for motion tracking. The radio section must be ultra low power e.g. sub 1 mW in order not to drain the limited battery capacity. The radio must also be small in size e.g. less than 5 x 5 mm so that the overall speck size is small. Also, the radio must still be able to operate over a range of at least a metre so as to allow radio contact between, for example, rooms or relatively distant specks. The unsuitability of conventional homodyne topologies to WSNs is discussed and more efficient methods of modulation (On-Off Keying) and demodulation (non-coherent) are presented. Furthermore, it is shown how Super-Regenerative Receivers (SRR) can be used to achieve relatively large output voltages for small input powers. This is important because baseband Op-Amps connected at the RF receiver output generally cannot amplify small signals at the input without the output being saturated in noise (10mV is the smallest measured input for 741 Op-Amp). Instrumentation amplifiers are used in this work as they can amplify signals below 1mV. The thesis details the analysis and design of basic RF building blocks: amplifiers, oscillators, switches and detectors. It also details how the circuits can be put together to make transceivers as well as describing various strategies to lower power consumption. In addition, novel techniques in both circuit and system design are presented which allow the power consumption of the radio to be reduced by as much as 97% whilst still retaining adequate performance. These techniques are based on duty cycling the transmitter and receiver and are possible because of the discontinuous nature of the On-Off Keying signal. In order to ease the sensitivity requirements of the baseband receive amplifier a design methodology for large output voltage receivers is presented. The designed receiver is measured to give a 5 mV output for an input power of -90 dBm and yet consumes less than 0.7 mW. There is also an appendix on the non linear modelling of the Glasgow University 50nm InP meta-morphic High Electron Mobility Transistor (50nm mHEMT) and one on the non linear modelling of a commercial Step Recovery diode (SRD). Models for the 50 nm mHEMT and the SRD are useful in the analysis, simulation and design of oscillators and pulse generators respectively

RF TRANSCEIVER DESIGN FOR WIRELESS SENSOR NETWORKS

Ph.DDOCTOR OF PHILOSOPH

Micropower Impulse Radio For Remote Controlled Insect Flight

Insects have remarkable strength and stamina compared to their body mass and fly and manuver effortlessly in ways that are impossible for present day robotic flyers. Therefore, efforts to control and direct flying insects for our own purposes have a huge potential payoff. One such effort, discussed in this dissertation, concerns the control of a Manduca Sexta moth by sending commands by radio to neural probes implanted in the thorax. The electronics hardware represents a major challenge in itself because the moth can carry only 700 milligrams, most of which is occupied by a small watch-battery. Ultimately, the moth must carry not only a radio receiver to pick up commands sent by the controller, but also a transmitter to return gathered information and fulfill its mission. Commercial "low-power", burst-mode radios have proven inadeqate because the battery cannot satisfy their peak power consumption. Instead, this dissertation focuses on the development of an alternative "impulse radio", which consumes power only during the ~100 picosecond interval required to generate a microwave pulse. The specific transmitter architecture presented here uses a nonlinear transmission line to directly convert digital signals provided by a microcontroller into microwave pulses broadcast by an antenna. This dissertation discusses (1) the background and theory of impulse-radios and (2) nonlinear transmission lines, (3) circuit board prototypes and (4) a CMOS implementation of the trans- mitter, (5) a study of the wireless link between the moth and its controller, as well as (6) efforts to implement the radio using light-weight, inexpensive plastic and polymer materials, before (7) reflecting on the potential of the new transmitter and possible directions for future work

A Mixed-Signal Demodulator for a Low-Complexity IR-UWB Receiver: Methodology, Simulation and Design

This works presents an integrated 0.18μm CMOS 2-PPM demodulator based on a switched capacitor network for an Energy Detection Impulse-Radio UWB receiver. The circuit has been designed using a top-down methodology that allows to discover the impact of low-level non-idealities on system-level performance. Through the use of a mixed signal simulation environment, performance figures have been obtained which helped evaluate the influence at system-level of the non-idealities of the most critical block. Results show that the circuit allows the replacement of the ADC typically employed in Energy Detection receivers and provides about infinite equivalent quantization resolution. The demodulator achieves 190 pJ/bit at 1.8V

Three-Port Bi-Directional DC–DC Converter with Solar PV System Fed BLDC Motor Drive Using FPGA

The increased need for renewable energy systems to generate power, store energy, and connect energy storage devices with applications has become a major challenge. Energy storage using batteries is most appropriate for energy sources like solar, wind, etc. A non-isolated three-port DC–DC-converter energy conversion unit is implemented feeding the brushless DCmotor drive. In this paper, a non-isolated three-port converter is designed and simulated for battery energy storage, interfaced with an output drive. Based on the requirements, the power extracted from the solar panel during the daytime is used to charge the batteries through the three-port converter. The proposed three-port converter is analyzed in terms of operating principles and power flow. An FPGA-based NI LabView PXI with SbRio interface is used to develop the suggested approach’s control hardware, and prototype model results are obtained to test the proposed three-port converter control system’s effectiveness and practicality. The overall efficiency of the converter’s output improves as a result. The success rate is 96.5 percent while charging an ESS, 98.1 percent when discharging an ESS, and 95.7 percent overall