A reconfigurable dual output low power digital PWM power converter

This versatile power converter controller provides dual outputs at a fixed switching frequency and can regulate either output voltage or target system delay (using an external L-C filter). In the voltage regulation mode, the output voltage is monitored with an A/D converter, and the feedback compensation network is implemented digitally. The generation of the PWM signal is done with a hybrid delay line/counter approach, which saves power and area relative to previous implementations. Power devices are included on chip to create the two independently regulated output PWM signals. The key features of this design are its low power dissipation, reconfigurability, use of either delay or voltage feedback, and multiple outputs

Topology Derivation and Development of Non-Isolated Three-port Converters for DC Microgrids

Currently, three-port converters (TPCs) are gaining popularity in applications which integrate renewable energies, such as photovoltaics and wind, and energy storage elements, such as batteries and supercapacitors with load. This is due to the advantages of a single power conversion stage between any two ports for better conversion efficiency and a highly integrated structure for compactness. Most of the reported TPCs focus on the consuming load. However, there are applications such as hybrid-electric vehicle braking systems and DC microgrids which have power generating capability. A typical example is battery charging in a DC microgrid. When the photovoltaics has inadequate power to charge the battery, the TPCs that consider only consuming load need an extra DC/DC converter for the DC bus to charge the battery. Three-winding transformers associated with full-bridge configurations as the basis for TPCs can fulfill the purpose of bi-directional power flow between any two ports. However, bulkiness of transformers and the need for more switches and associated control mechanisms increases the converter complexity, volume and cost. Solutions for integrating a regenerative load in NITPCs are still limited. This research work focuses on the development of non-isolated three-port converters (NITPCs), as they are capable of driving a regenerative load while offering a compact solution. The study includes a systematic approach to deriving a family of NITPCs. They combine different commonly known power converters in an integrated manner while considering the voltage polarity, voltage levels among the ports and overall voltage conversion ratio. The derived converter topologies allow for all possible power flow combinations among the sources and load while preserving the single power processing feature of the TPC. A design example of a boost converter based TPC with a bi-directional buck converter is reported. In addition, a novel single-inductor NITPC is proposed. It is a further integrated topology according to the aforementioned design example where only one inductor is required instead of two, and the number of power transistors remains the same. The detailed topological derivation, operation principles, steady-state analysis, simulation results and experiment results are given to verify the proposed NITPCs

Integrated circuits for efficient power delivery using pulse-width-modulation

Circuits and architectures for efficient power delivery have become crucial in emerging smart systems. Switching power amplifiers (PA) are very attractive for such applications, because they exhibit better efficiency compared to linear PA designs, due to saturated operation. Switching PAs also allow for utilization of deep submicron CMOS technologies, due to which these designs can be easily integrated with digital circuits, and can benefit from process scaling, in performance as well as in area. Pulse-width-modulation (PWM) is commonly used with switching PAs. A PWM signal typically employs a high-frequency switching pulse waveform as a carrier signal, wherein the pulse-width or duty-cycle of each pulse is modulated by a given low-frequency input signal. The carrier frequency can vary from several kHz to GHz, and is typically determined by the target application. In this thesis, efficient power-delivery circuits that use PWM with switching class-D stages are presented. Advanced circuit techniques, as well as architectures for PWM are proposed to enhance efficiency and circumvent the limitations of conventional architectures. A digitally-intensive transmitter using RF-PWM with a class-D PA is described in the first part of the thesis. The use of carrier switching for alleviating the dynamic range limitation that can be observed in classical RF-PWM implementations is introduced. The approach employs the full carrier frequency for half of the amplitude range, and the second harmonic of half of the carrier frequency, for the remainder of the amplitude range. This concept not only allows the transmitter to drive modulated signals with large peak-to-average power ratio (PAPR), but also improves the back-off efficiency due to reduced switching losses in the half carrier-frequency mode. A glitch-free phase selector is proposed that removes the deleterious glitches that can occur at the input data transitions. The phase-selector also prevents D flip-flop setup-and-hold time violations. The transmitter has been implemented in a 130-nm CMOS process. The measured peak output power and power-added-efficiency (PAE) are 25.6 dBm and 34%, respectively. While driving 802.11g 20-MHz 64-QAM OFDM signals, the average measured output power is 18.3 dBm and the PAE is 16%, with an EVM of -25.5 dB. The second part of the thesis describes a high-speed driver that provides a PWM output using a class-D PA. A PLL-based architecture is employed which eliminates the requirement for a precise ramp or triangular signal generator, and a high-speed comparator, which are typically used for PWM generation. Multi-level signaling is proposed to enhance back-off as well as peak efficiency, which is critical for signals with high PAPR. A differential, folded PWM scheme is introduced to achieve highly linear operation. 3-level operation is achieved without the requirement for additional supply source or sink paths, while 5-level operation is achieved with additional supply source and sink paths, compared to 2-level operation. The PWM driver has been implemented in a 130-nm CMOS process and can operate with a switching frequency of 40-to-170 MHz. For 2/3/5-level PA operation, with a 500 kHz sinusoidal input and 60 MHz switching frequency, the measured THD is -61/-62/-53 dB and corresponding efficiency is 71/83/86% with 175/200/220 mW output power level, respectively. Performance has also been verified for 2/3-level PA operation with a high PAPR signal with 500 kHz bandwidth. While intended as a general purpose amplifier, the approach is well-suited for applications such as power-line communications (PLC). The final part of the thesis introduces an efficient buck/buck-boost reconfigurable LED driver that supports PWM and PFM operation. The driver is based on peak current control. Rectified sin as well as sin² functions are employed in the reference signal to improve the power factor (PF) and total harmonic distortion (THD) of the buck and buck-boost converters. The design ensures that the peak of the inductor current maintains a constant level that is invariant for different AC line voltages. The operating mode of the design can be changed between PWM and PFM. The LED driver has been implemented in a 130-nm CMOS process. PF and THD are improved when the proposed reference is employed, and peak PF and lowest THD are 0.995/0.983/0.996 and 7.8/6.2/3.5% for the buck (PWM), buck (PFM), buck-boost (PFM) cases, respectively. The corresponding peak efficiency for the three cases is 88/92/91%, respectively.Electrical and Computer Engineerin