Developing Model-Based Design Evaluation for Pipelined A/D Converters

This paper deals with a prospective approach of modeling, design evaluation and error determination applied to pipelined A/D converter architecture. In contrast with conventional ADC modeling algorithms targeted to extract the maximum ADC non-linearity error, the innovative approach presented allows to decompose magnitudes of individual error sources from a measured or simulated response of an ADC device. Design Evaluation methodology was successfully applied to Nyquist rate cyclic converters in our works [13]. Now, we extend its principles to pipelined architecture. This qualitative decomposition can significantly contribute to the ADC calibration procedure performed on the production line in term of integral and differential nonlinearity. This is backgrounded by the fact that the knowledge of ADC performance contributors provided by the proposed method helps to adjust the values of on-chip converter components so as to equalize (and possibly minimize) the total non-linearity error. In this paper, the design evaluation procedure is demonstrated on a system design example of pipelined A/D converter. Significant simulation results of each stage of the design evaluation process are given, starting from the INL performance extraction proceeded in a powerful Virtual Testing Environment implemented in Maple™ software and finishing by an error source simulation, modeling of pipelined ADC structure and determination of error source contribution, suitable for a generic process flow

A digital high-dynamic-range CMOS image sensor with multi-integration and pixel readout request

A novel principle has been developed to build an ultra wide dynamic range digital CMOS image sensor. Multiple integrations are used to achieve the required dynamic. Its innovative readout system allows a direct capture of the final image from the different exposure time with no need of external reconstruction. The sensor readout system is entirely digital, implementing an in-pixel ADC. Realized in the STMicroelectronics 0.13μm CMOS standard technology, the 10μm x 10μm pixels contain 42 transistors with a fill factor of 25%. The sensor is able to capture more than 120dB dynamic range scenes at video rate

Development of an instrument for real-time computation of indicated mean effective pressure

A new instrument capable of computing in real time the per-cycle indicated mean effective pressure (IMEP) of internal combustion engines and compressors was designed and tested. The values of IMEP obtained with the new instrument were found to be in excellent agreement with values obtained by previous postrun data reduction techniques

A mobile data acquisition system

A mobile data aquisition (MobiDAQ) was developed for the ATLAS central hadronic calorimeter (TileCal). MobiDAQ has been designed in order to test the functionalities of the TileCal front-end electronics and to acquire calibration data before the final back-end electronics were built and tested. MobiDAQ was also used to record the first cosmic ray events acquired by an ATLAS subdetector in the underground experimental area

An antenna switching based NOMA scheme for IEEE 802.15.4 concurrent transmission

This paper introduces a Non-Orthogonal Multiple Access (NOMA) scheme to support concurrent transmission of multiple IEEE 802.15.4 packets. Unlike collision avoidance Multiple Access Control (MAC), concurrent transmission supports Concurrent-MAC (C-MAC) where packet collision is allowed. The communication latency can be reduced by C-MAC because a user can transmit immediately without waiting for the completion of other users’ transmission. The big challenge of concurrent transmission is that error free demodulation of multiple collided packets hardly can be achieved due to severe Multiple Access Interference (MAI). To improve the demodulation performance with MAI presented, we introduce an architecture with multiple switching antennas sharing a single analog transceiver to capture spatial character of different users. Successive Interference Cancellation (SIC) algorithm is designed to separate collided packets by utilizing the spatial character. Simulation shows that at least five users can transmit concurrently to the SIC receiver equipped with eight antennas without sacrificing Packet Error Rate

Low power VCO-based analog-to-digital conversion

textThis dissertation presents novel two stage ADC architecture with a VCO based second stage. With the scaling of the supply voltages in modern CMOS process it is difficult to design high gain operational amplifiers needed for traditional voltage domain two-stage analog to digital converters. However time resolution continues to improve with the advancement in CMOS technology making VCO-based ADC more attractive. The nonlinearity in voltage-to-frequency transfer function is the biggest challenge in design of VCO based ADC. The hybrid approach used in this work uses a voltage domain first stage to determine the most significant bits and uses a VCO based second stage to quantize the small residue obtained from first stage. The architecture relaxes the gain requirement on the the first stage opamp and also relaxes the linearity requirements on the second stage VCO. The prototype ADC built in 65nm CMOS process achieves 63.7dB SNDR in 10MHz bandwidth while only consuming 1.1mW of power. The performance of the prototype chip is comparable to the state-of-art in terms of figure-of-merit but this new architecture uses significantly less circuit area.Electrical and Computer Engineerin