120 research outputs found
Reconfigurable architectures for the next generation of mobile device telecommunications systems
Mobile devices have become a dominant tool in our daily lives. Business and
personal usage has escalated tremendously since the emergence of smartphones
and tablets. The combination of powerful processing in mobile devices, such as
smartphones and the Internet, have established a new era for communications
systems. This has put further pressure on the performance and efficiency of
telecommunications systems in delivering the aspirations of users. Mobile device
users no longer want devices that merely perform phone calls and messaging.
Rather, they look for further interactive applications such as video streaming,
navigation and real time social interaction. Such applications require a new set of
hardware and standards. The WiFi (IEEE 802.11) standard has been at the forefront
of reliable and high-speed internet access telecommunications. This is due to its
high signal quality (quality of service) and speed (throughput). However, its limited
availability and short range highlights the need for further protocols, in particular
when far away from access points or base stations. This led to the emergence of 3G
followed by 4G and the upcoming 5G standard that, if fully realised, will provide
another dimension in “anywhere, anytime internet connectivity.” On the other
hand, the WiMAX (IEEE 802.16) standard promises to exceed the WiFi signal
coverage range. The coverage range could be extended to kilometres at least with a
better or similar WiFi signal level.
This thesis considers a dynamically reconfigurable architecture that is capable of
processing various modules within telecommunications systems. Forward error
correction, coder and navigation modules are deployed in a unified low power
communication platform. These modules have been selected since they are among
those with the highest demand in terms of processing power, strict processing time
or throughput. The modules are mainly realised within WiFi and WiMAX systems
in addition to global positioning systems (GPS). The idea behind the selection of
these modules is to investigate the possibility of designing an architecture capable
of processing various systems and dynamically reconfiguring between them. The
GPS system is a power-hungry application and, at the same time, it is not needed
all of the time. Hence, one key idea presented in this thesis is to effectively exploit
the dynamic reconfiguration capability so as to reconfigure the architecture (GPS)
when it is not needed in order to process another needed application or function
such as WiFi or WiMAX. This will allow lower energy consumption and the
optimum usage of the hardware available on the device.
This work investigates the major current coarse-grain reconfigurable architectures.
A novel multi-rate convolution encoder is then designed and realised as a
reconfigurable fabric. This demonstrates the ability to adapt the algorithms
involved to meet various requirements. A throughput of between 200 and 800
Mbps has been achieved for the rates 1/2 to 7/8, which is a great achievement for
the proposed novel architecture. A reconfigurable interleaver is designed as a
standalone fabric and on a dynamically reconfigurable processor. High throughputs
exceeding 90 Mbps are achieved for the various supported block sizes. The Reed
Solomon coder is the next challenging system to be designed into a dynamically
reconfigurable processor. A novel Galois Field multiplier is designed and
integrated into the developed Reed Solomon reconfigurable processor. As a result
of this work, throughputs of 200Mbps and 93Mbps respectively for RS encoding
and decoding are achieved. A GPS correlation module is also investigated in this
work. This is the main part of the GPS receiver responsible for continuously
tracking GPS satellites and extracting messages from them. The challenging aspect
of this part is its real-time nature and the associated critical time constraints. This
work resulted in a novel dynamically reconfigurable multi-channel GPS correlator
with up to 72 simultaneous channels.
This work is a contribution towards a global unified processing platform that is
capable of processing communication-related operations efficiently and
dynamically with minimum energy consumption
Energy-Efficient Computing for Mobile Signal Processing
Mobile devices have rapidly proliferated, and deployment of handheld devices continues to increase at a spectacular rate. As today's devices not only support advanced signal processing of wireless communication data but also provide rich sets of applications, contemporary mobile computing requires both demanding computation and efficiency. Most mobile processors combine general-purpose processors, digital signal processors, and hardwired application-specific integrated circuits to satisfy their high-performance and low-power requirements. However, such a heterogeneous platform is inefficient in area, power and programmability. Improving the efficiency of programmable mobile systems is a critical challenge and an active area of computer systems research.
SIMD (single instruction multiple data) architectures are very effective for data-level-parallelism intense algorithms in mobile signal processing. However, new characteristics of advanced wireless/multimedia algorithms require architectural re-evaluation to achieve better energy efficiency. Therefore, fourth generation wireless protocol and high definition mobile video algorithms are analyzed to enhance a wide-SIMD architecture. The key enhancements include 1) programmable crossbar to support complex data alignment, 2) SIMD partitioning to support fine-grain SIMD computation, and 3) fused operation to support accelerating frequently used instruction pairs.
Near-threshold computation has been attractive in low-power architecture research because it balances performance and power. To further improve energy efficiency in mobile computing, near-threshold computation is applied to a wide SIMD architecture. This proposed near-threshold wide SIMD architecture-Diet SODA-presents interesting architectural design decisions such as 1) very wide SIMD datapath to compensate for degraded performance induced by near-threshold computation and 2) scatter-gather data prefetcher to exploit large latency gap between memory and the SIMD datapath. Although near-threshold computation provides excellent energy efficiency, it suffers from increased delay variations. A systematic study of delay variations in near-threshold computing is performed and simple techniques-structural duplication and voltage/frequency margining-are explored to tolerate and mitigate the delay variations in near-threshold wide SIMD architectures.
This dissertation analyzes representative wireless/multimedia mobile signal processing algorithms, proposes an energy-efficient programmable platform, and evaluates performance and power. A main theme of this dissertation is that the performance and efficiency of programmable embedded systems can be significantly improved with a combination of parallel SIMD and near-threshold computations.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/86356/1/swseo_1.pd
Self-Healing Cellular Automata to Correct Soft Errors in Defective Embedded Program Memories
Static Random Access Memory (SRAM) cells in ultra-low power Integrated Circuits (ICs) based on nanoscale Complementary Metal Oxide Semiconductor (CMOS) devices are likely to be the most vulnerable to large-scale soft errors. Conventional error correction circuits may not be able to handle the distributed nature of such errors and are susceptible to soft errors themselves. In this thesis, a distributed error correction circuit called Self-Healing Cellular Automata (SHCA) that can repair itself is presented. A possible way to deploy a SHCA in a system of SRAM-based embedded program memories (ePM) for one type of chip multi-processors is also discussed. The SHCA is compared with conventional error correction approaches and its strengths and limitations are analyzed
Architecture and Analysis for Next Generation Mobile Signal Processing.
Mobile devices have proliferated at a spectacular rate, with more than 3.3 billion active cell phones in the world. With sales totaling hundreds of billions every year, the mobile phone has arguably become the dominant computing platform, replacing the personal computer. Soon, improvements to today’s smart phones, such as high-bandwidth internet access, high-definition video processing, and human-centric interfaces that integrate voice recognition and video-conferencing will be commonplace. Cost effective and power efficient support for these applications will be required.
Looking forward to the next generation of mobile computing, computation requirements will increase by one to three orders of magnitude due to higher
data rates, increased complexity algorithms, and greater computation diversity but the power requirements will be
just as stringent to ensure reasonable battery lifetimes. The design of the next generation of mobile platforms must address three critical challenges: efficiency, programmability, and adaptivity. The computational efficiency of existing solutions is inadequate and straightforward scaling by increasing the number of cores or the amount of data-level parallelism will not suffice. Programmability provides the opportunity for a single platform to support multiple applications and even multiple standards within each application domain. Programmability also provides: faster time to market as hardware and software development can proceed in parallel; the ability to fix bugs and add features after manufacturing; and, higher chip volumes as a single platform can support a family of mobile devices. Lastly, hardware adaptivity is necessary to maintain efficiency as the computational characteristics of the applications change. Current solutions are tailored specifically for wireless signal processing algorithms, but lose their efficiency when other application domains like high definition video are processed.
This thesis addresses these challenges by presenting analysis of next generation mobile signal processing applications and proposing an advanced signal processing architecture to deal with the stringent requirements. An application-centric design approach is taken to design our architecture. First, a next generation wireless protocol and high definition video is analyzed and algorithmic characterizations discussed. From these characterizations, key architectural implications are presented, which form the basis for the advanced signal processor architecture, AnySP.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/86344/1/mwoh_1.pd
Survey of FPGA applications in the period 2000 – 2015 (Technical Report)
Romoth J, Porrmann M, Rückert U. Survey of FPGA applications in the period 2000 – 2015 (Technical Report).; 2017.Since their introduction, FPGAs can be seen in more and more different fields of applications. The key advantage is the combination of software-like flexibility with the performance otherwise common to hardware. Nevertheless, every application field introduces special requirements to the used computational architecture. This paper provides an overview of the different topics FPGAs have been used for in the last 15 years of research and why they have been chosen over other processing units like e.g. CPUs
State of the art baseband DSP platforms for Software Defined Radio: A survey
Software Defined Radio (SDR) is an innovative approach which is becoming a more and more promising technology for future mobile handsets. Several proposals in the field of embedded systems have been introduced by different universities and industries to support SDR applications. This article presents an overview of current platforms and analyzes the related architectural choices, the current issues in SDR, as well as potential future trends.Peer reviewe
The implementation of an LDPC decoder in a Network on Chip environment
The proposed project takes origin from a cooperation initiative named NEWCOM++ among
research groups to develop 3G wireless mobile system. This work, in particular, tries to focuse on
the communication errors arising on a message signal characterized by working under WiMAX
802.16e standard. It will be shown how this last wireless generation protocol needs a specific
flexible instrumentation and why an LDPC error correction code suitable in order to respect the
quality restrictions. A chapter will be dedicated to describe, not from a mathematical point of view,
the LDPC algorithm theory and how it can be graphically represented to better organize the
decodification process.
The main objective of this work is to validate the PHAL-concept when addressing a
complex and computationally intensive design like the LDPC encoder/decoder. The expected results
should be both conceptual; identifying the lacks on the PHAL concept when addressing a real
problem; and second to determine the overhead introduced by PHAL in the implementation of a
LDPC decoder.
The mission is to build a NoC (Network on Chip) able to perform the same task of a general
purpose processor, but in less time and with better efficiency, in terms of component flexibility and
throughput. The single element of the network is a basic processor element (PE) formed by the
union of two separated components: a special purpose processor ASIP, the responsible of the input
data LDPC decoding, and the router component PHAL, checking incoming data packets and
scanning the temporization of tasks execution.
Supported by a specific programming tool, the ASIP has been completely designed, from the
architecture resources to the instruction set, through a language like C. Realized in this SystemC
code and converted in VHDL language, it's been synthesized as to fit onto an FPGA of the Xilinx
Virtex-5 family. Although the main purpose regards the making of an application as flexible as
possible, a WiMAX-orientated LDPC implemented on a FPGA saves space and resources, choosing
the one that best suits the project synthesis. This is because encoders and decoders will have to find
room in the communication tools (e.g. modems) as best as possible.
The whole network scenary has been mounted through a Linux application, acting as a
master element. The entire environment will require the use of VPI libraries and components able to
manage the communication protocols and interfacing mechanisms
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