Intra Region Routing

The custom integrated circuit routing problem normally requires partitioning into rectangular routing regions. Natural partitions usually result in regions that form both channels and areas . This dissertation introduces several new channel and area routing algorithms and measures their performance. A formal description of the channel routing problem is presented and a relationship is established between the selection of intervals for each track and the number of tracks in the completed channel. This relationship is used as an analysis tool that leads to the development of two new and highly effective channel routing algorithms: the Revised and LCP algorithms. The performance of these algorithms is compared against the Dogleg, Greedy, and several area routing algorithms over sets of randomly generated channels. The results indicate performance increases ranging from 2.74 to 34 times, depending on the characteristics of the channel. In area routing, a new Degree of Freedom (DOF) based algorithm is developed that is straightforward to implement, is extensible to multipoint nets and reports if a path does not exist to complete the net. The quality of area routing algorithms is measured by the difficulty of the areas that can be successfully routed over sets of randomly generated areas. An extended definition of Manhattan Area Measure (MAM) is introduced as a measure of the difficulty of completing the wiring for areas with multipoint nets. The results show that the DOF algorithm has higher completion rates than the Lee algorithm. This difference is greatest in areas with high aspect ratios. A new measure of the difficulty of an area is developed that places upper bounds on the performance of area routing algorithms. In areas with low aspect ratios, the drop in algorithm completion rates is closely related to this upper bound

A Density-Based General Greedy Channel Routing Algorithm in VLSI Design Automation.

One of the most important forms of routing strategies is called channel routing . This approach allows us to reduce the extremely difficult VLSI layout problem to a collection of simpler subproblems. For channel routing problems, most frequently mentioned heuristic algorithms use parameters derived from experiments to approach the routing solution without carefully considering the effect of each selected wire segment to the final routing solution. In this dissertation, we propose a new channel routing algorithm in the two-layer restricted-Manhattan routing model (2-RM) in detail. There are three phases involved in developing the new routing algorithm. In the first phase, we distinguish one type of wire from the others using some optimality criteria, which makes the selection of a set of best horizontal wire segments for a track more effective so that good performance of the generated routing solutions can be achieved. In the second phase, we develop a theoretical framework related to two major data structures, column density and vertical constraint graph, which effectively improves search efficiency and routing performance. Finally in the third phase, we develop an efficient powerful heuristic channel routing algorithm based on the concepts shown in phase one and the theoretical framework proposed in phase two. We highlight the application of our algorithm to the channel routing problems in the three-layer restricted-Manhattan overlap (3-RM-O) and three-layer Manhattan overlay (3-M-O) routing models. On many tests we have conducted on the examples known in the literature, our algorithm has performed as well or better than the existing algorithms in both 2-RM and 3-M-O routing models. Our experiments show that our approach has the potential to outperform other algorithms in other routing models

Integrating LEO Satellite Constellations into Internet Backbone

Low Earth Orbit (LEO) satellite constellations have been used for ubiquitous and flexible Internet access services. However, a number of problems related to the integration of terrestrial with satellite hosts should be resolved for the effective exploitation of LEO constellations. LEO constellations are different from terrestrial Internet because of its special properties, which result in a lot of problems. A key issue is how to route Internet packets to the LEO constellation. In the thesis (1) the background of LEO constellations was introduced; (2) the obstacles of routing between the satellites and Internet were outlined; (3) The particular problem, which must be solved, is the routing burst stream traffic in LEO satellite constellations. Two novel routing algorithmsCControl Route Transmission (CRT) and CRT with bandwidth allocation (BCRT)Cwere utilized to address the bursts routing problem. CRT is an adaptive protocol which is able to minimize the congestion in the constellations. BCRT is a CRT extension which is allowed to class the traffic (e.g. video) with different QoS requirements and guarantees. Both of CRT and BCRT work in time epochs. Routes are computed on the basis of a directed weighted graph representing the global traffic traveling in the constellations. Both CRT and BCRT were evaluated via simulation and compared with other proposals in the literatures. The results showed that CRT is a simple algorithm, but the strategy produced by CRT could avoid the congestion and enhance the global resource usage in different traffic conditions. Moreover, the explicit reservation and reroute of BCRT greatly improve the performance of CRT. In particular, the dropping rate of BCRT is very low and the average delivery time is comparable with other proposals in the literatures.Low Earth Orbit (LEO) satellite constellations have been used for ubiquitous and flexible Internet access services. However, a number of problems related to the integration of terrestrial with satellite hosts should be resolved for the effective exploitation of LEO constellations. LEO constellations are different from terrestrial Internet because of its special properties, which result in a lot of problems. A key issue is how to route Internet packets to the LEO constellation. In the thesis (1) the background of LEO constellations was introduced; (2) the obstacles of routing between the satellites and Internet were outlined; (3) The particular problem, which must be solved, is the routing burst stream traffic in LEO satellite constellations. Two novel routing algorithmsCControl Route Transmission (CRT) and CRT with bandwidth allocation (BCRT)Cwere utilized to address the bursts routing problem. CRT is an adaptive protocol which is able to minimize the congestion in the constellations. BCRT is a CRT extension which is allowed to class the traffic (e.g. video) with different QoS requirements and guarantees. Both of CRT and BCRT work in time epochs. Routes are computed on the basis of a directed weighted graph representing the global traffic traveling in the constellations. Both CRT and BCRT were evaluated via simulation and compared with other proposals in the literatures. The results showed that CRT is a simple algorithm, but the strategy produced by CRT could avoid the congestion and enhance the global resource usage in different traffic conditions. Moreover, the explicit reservation and reroute of BCRT greatly improve the performance of CRT. In particular, the dropping rate of BCRT is very low and the average delivery time is comparable with other proposals in the literatures

Efficient Interconnection Schemes for VLSI and Parallel Computation

This thesis is primarily concerned with two problems of interconnecting components in VLSI technologies. In the first case, the goal is to construct efficient interconnection networks for general-purpose parallel computers. The second problem is a more specialized problem in the design of VLSI chips, namely multilayer channel routing. In addition, a final part of this thesis provides lower bounds on the area required for VLSI implementations of finite-state machines. This thesis shows that networks based on Leiserson\u27s fat-tree architecture are nearly as good as any network built in a comparable amount of physical space. It shows that these universal networks can efficiently simulate competing networks by means of an appropriate correspondence between network components and efficient algorithms for routing messages on the universal network. In particular, a universal network of area A can simulate competing networks with O(lg^3A) slowdown (in bit-times), using a very simple randomized routing algorithm and simple network components. Alternatively, a packet routing scheme of Leighton, Maggs, and Rao can be used in conjunction with more sophisticated switching components to achieve O(lg^2 A) slowdown. Several other important aspects of universality are also discussed. It is shown that universal networks can be constructed in area linear in the number of processors, so that there is no need to restrict the density of processors in competing networks. Also results are presented for comparisons between networks of different size or with processors of different sizes (as determined by the amount of attached memory). Of particular interest is the fact that a universal network built from sufficiently small processors can simulate (with the slowdown already quoted) any competing network of comparable size regardless of the size of processors in the competing network. In addition, many of the results given do not require the usual assumption of unit wire delay. Finally, though most of the discussion is in the two-dimensional world, the results are shown to apply in three dimensions by way of a simple demonstration of general results on graph layout in three dimensions. The second main problem considered in this thesis is channel routing when many layers of interconnect are available, a scenario that is becoming more and more meaningful as chip fabrication technologies advance. This thesis describes a system MulCh for multilayer channel routing which extends the Chameleon system developed at U. C. Berkeley. Like Chameleon, MulCh divides a multilayer problem into essentially independent subproblems of at most three layers, but unlike Chameleon, MulCh considers the possibility of using partitions comprised of a single layer instead of only partitions of two or three layers. Experimental results show that MulCh often performs better than Chameleon in terms of channel width, total net length, and number of vias. In addition to a description of MulCh as implemented, this thesis provides improved algorithms for subtasks performed by MulCh, thereby indicating potential improvements in the speed and performance of multilayer channel routing. In particular, a linear time algorithm is given for determining the minimum width required for a single-layer channel routing problem, and an algorithm is given for maintaining the density of a collection of nets in logarithmic time per net insertion. The last part of this thesis shows that straightforward techniques for implementing finite-state machines are optimal in the worst case. Specifically, for any s and k, there is a deterministic finite-state machine with s states and k symbols such that any layout algorithm requires (ks lg s) area to lay out its realization. For nondeterministic machines, there is an analogous lower bound of (ks^2) area

Intelligent approaches to VLSI routing

Very Large Scale Integrated-circuit (VLSI) routing involves many large-size and complex problems and most of them have been shown to be NP-hard or NP-complete. As a result, conventional approaches, which have been successfully used to handle relatively small-size routing problems, are not suitable to be used in tackling large-size routing problems because they lead to \u27combinatorial explosion\u27 in search space. Hence, there is a need for exploring more efficient routing approaches to be incorporated into today\u27s VLSI routing system. This thesis strives to use intelligent approaches, including symbolic intelligence and computational intelligence, to solve three VLSI routing problems: Three-Dimensional (3-D) Shortest Path Connection, Switchbox Routing and Constrained Via Minimization. The 3-D shortest path connection is a fundamental problem in VLSI routing. It aims to connect two terminals of a net that are distributed in a 3-D routing space subject to technological constraints and performance requirements. Aiming at increasing computation speed and decreasing storage space requirements, we present a new A* algorithm for the 3-D shortest path connection problem in this thesis. This new A*algorithm uses an economical representation and adopts a novel back- trace technique. It is shown that this algorithm can guarantee to find a path if one exists and the path found is the shortest one. In addition, its computation speed is fast, especially when routed nets are spare. The computational complexities of this A* algorithm at the best case and the worst case are O(Ɩ) and 0(Ɩ3), respectively, where Ɩ is the shortest path length between the two terminals. Most importantly, this A\u27 algorithm is superior to other shortest path connection algorithms as it is economical in terms of storage space requirement, i.e., 1 bit/grid. The switchbox routing problem aims to connect terminals at regular intervals on the four sides of a rectangle routing region. From a computational point of view, the problem is NP-hard. Furthermore, it is extremely complicated and as the consequence no existing algorithm can guarantee to find a solution even if one exists no matter how high the complexity of the algorithm is. Previous approaches to the switch box routing problem can be divided into algorithmic approaches and knowledge-based approaches. The algorithmic approaches are efficient in computational time, but they are unsucessful at achieving high routing completion rate, especially for some dense and complicated switchbox routing problems. On the other hand, the knowledge-based approaches can achieve high routing completion rate, but they are not efficient in computation speed. In this thesis we present a hybrid approach to the switchbox routing problem. This hybrid approach is based on a new knowledge-based routing technique, namely synchronized routing, and combines some efficient algorithmic routing techniques. Experimental results show it can achieve the high routing completion rate of the knowledge-based approaches and the high efficiency of the algorithmic approaches. The constrained via minimization is an important optimization problem in VLSI routing. Its objective is to minimize the number of vias introduced in VLSI routing. From computational perspective, the constrained via minimization is NP-complete. Although for a special case where the number of wire segments splits at a via candidate is not more than three, elegant theoretical results have been obtained. For a general case in which there exist more than three wire segment splits at a via candidate few approaches have been proposed, and those approaches are only suitable for tackling some particular routing styles and are difficult or impossible to adjust to meet practical requirements. In this thesis we propose a new graph-theoretic model, namely switching graph model, for the constrained via minimization problem. The switching graph model can represent both grid-based and grid less routing problems, and allows arbitrary wire segments split at a via candidate. Then on the basis of the model, we present the first genetic algorithm for the constrained via minimization problem. This genetic algorithm can tackle various kinds of routing styles and be configured to meet practical constraints. Experimental results show that the genetic algorithm can find the optimal solutions for most cases in reasonable time