Fully Synthesizable, Rail-to-Rail Dynamic Voltage Comparator for Operation down to 0.3V

A novel rail-to-rail dynamic voltage comparator is presented in this paper. The proposed circuit is fully synthesizable, as it can be designed with automated digital design flows and standard cells, and can operate at very low voltages down to deep sub-threshold. Post-layout simulations show correct operation for rail-to-rail common-mode inputs at a supply voltage VDD down to 0.3 V. At such voltage, the input offset voltage standard deviation is less than 28 mV (8 mV) over the rail-to-rail common-mode input range (around VDD/2). The digital nature of the comparator and its ability to operate down to deep sub-threshold voltages allow its full integration with standard-cell digital circuits in terms of both design and voltage domain. The ease of design, the low area and the voltage scalability make the proposed comparator very well suited for sensor nodes, integrated circuits for the Internet of Things and related applications

Ultra-Low-Power Sensors and Receivers for IoT Applications

The combination of ultra-low power analog front-ends and CMOS-compatible transducers enable new applications, such as environmental monitors, household appliances, health trackers, etc. that are seamlessly integrated into our daily lives. Furthermore, wireless connectivity allows many of these sensors to operate both independently and collectively. These techniques collectively fulfil the recent surge of internet-of-things (IoT) applications that have the potential to fundamentally change daily life for millions of people.In this dissertation, the circuit and system design of wireless receivers and sensors is presented that explores the challenges of implementing long lifespan, high accuracy, and large coverage range IoT sensor networks. The first is a wake-up receiver (WuRX), which continuously monitors the RF environment to wake up a higher-power radio upon detection of a predetermined RF signature. This work both improves sensitivity and reduces power over prior art through a multi-faceted design featuring an impedance transformation network with large passive voltage gain, an active envelope detector with high input impedance to facilitate large passive voltage gain, a low-power precision comparator, and a low-leakage digital baseband correlator.Although pushing the prior WuRX performance boundary by orders of magnitude, the first work shows moderate sensitivity, inferior temperature robustness, and large area with external lumped components. Thus, the second work shows a miniaturized WuRX that is temperature-compensated, yet still consumes only nano-watt power and millimeter area while operating at 9 GHz. To further reduce the area, a global common-mode feedback is utilized across the envelope detector and baseband amplifier that eliminates the need for off-chip ac-coupling components. Multiple temperature-compensation techniques are proposed to maintain constant bandwidth of the signal path and constant clock frequency. Both WuRXs operate at 0.4 V supply, consume near-zero power and achieve ~-70 dBm sensitivity.Lastly, the first reported CMOS 2-in-1 relative humidity and temperature sensor is presented. A unified analog front-end interfaces on-chip transducers and converts the inputs into a frequency vis a high-linearity frequency-locked loop. An incomplete-settling switched-capacitor-based Wheatstone bridge is proposed to sense the inputs in a power-efficient fashion

Ultra-low power mixed-signal frontend for wearable EEGs

Electronics circuits are ubiquitous in daily life, aided by advancements in the chip design industry, leading to miniaturised solutions for typical day to day problems. One of the critical healthcare areas helped by this advancement in technology is electroencephalography (EEG). EEG is a non-invasive method of tracking a person's brain waves, and a crucial tool in several healthcare contexts, including epilepsy and sleep disorders. Current ambulatory EEG systems still suffer from limitations that affect their usability. Furthermore, many patients admitted to emergency departments (ED) for a neurological disorder like altered mental status or seizures, would remain undiagnosed hours to days after admission, which leads to an elevated rate of death compared to other conditions. Conducting a thorough EEG monitoring in early-stage could prevent further damage to the brain and avoid high mortality. But lack of portability and ease of access results in a long wait time for the prescribed patients. All real signals are analogue in nature, including brainwaves sensed by EEG systems. For converting the EEG signal into digital for further processing, a truly wearable EEG has to have an analogue mixed-signal front-end (AFE). This research aims to define the specifications for building a custom AFE for the EEG recording and use that to review the suitability of the architectures available in the literature. Another critical task is to provide new architectures that can meet the developed specifications for EEG monitoring and can be used in epilepsy diagnosis, sleep monitoring, drowsiness detection and depression study. The thesis starts with a preview on EEG technology and available methods of brainwaves recording. It further expands to design requirements for the AFE, with a discussion about critical issues that need resolving. Three new continuous-time capacitive feedback chopped amplifier designs are proposed. A novel calibration loop for setting the accurate value for a pseudo-resistor, which is a crucial block in the proposed topology, is also discussed. This pseudoresistor calibration loop achieved the resistor variation of under 8.25%. The thesis also presents a new design of a curvature corrected bandgap, as well as a novel DDA based fourth-order Sallen-Key filter. A modified sensor frontend architecture is then proposed, along with a detailed analysis of its implementation. Measurement results of the AFE are finally presented. The AFE consumed a total power of 3.2A (including ADC, amplifier, filter, and current generation circuitry) with the overall integrated input-referred noise of 0.87V-rms in the frequency band of 0.5-50Hz. Measurement results confirmed that only the proposed AFE achieved all defined specifications for the wearable EEG system with the smallest power consumption than state-of-art architectures that meet few but not all specifications. The AFE also achieved a CMRR of 131.62dB, which is higher than any studied architectures.Open Acces

Study of Single-Event Transient Effects on Analog Circuits

Radiation in space is potentially hazardous to microelectronic circuits and systems such as spacecraft electronics. Transient effects on circuits and systems from high energetic particles can interrupt electronics operation or crash the systems. This phenomenon is particularly serious in complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) since most of modern ICs are implemented with CMOS technologies. The problem is getting worse with the technology scaling down. Radiation-hardening-by-design (RHBD) is a popular method to build CMOS devices and systems meeting performance criteria in radiation environment. Single-event transient (SET) effects in digital circuits have been studied extensively in the radiation effect community. In recent years analog RHBD has been received increasing attention since analog circuits start showing the vulnerability to the SETs due to the dramatic process scaling. Analog RHBD is still in the research stage. This study is to further study the effects of SET on analog CMOS circuits and introduces cost-effective RHBD approaches to mitigate these effects. The analog circuits concerned in this study include operational amplifiers (op amps), comparators, voltage-controlled oscillators (VCOs), and phase-locked loops (PLLs). Op amp is used to study SET effects on signal amplitude while the comparator, the VCO, and the PLL are used to study SET effects on signal state during transition time. In this work, approaches based on multi-level from transistor, circuit, to system are presented to mitigate the SET effects on the aforementioned circuits. Specifically, RHBD approach based on the circuit level, such as the op amp, adapts the auto-zeroing cancellation technique. The RHBD comparator implemented with dual-well and triple-well is studied and compared at the transistor level. SET effects are mitigated in a LC-tank oscillator by inserting a decoupling resistor. The RHBD PLL is implemented on the system level using triple modular redundancy (TMR) approach. It demonstrates that RHBD at multi-level can be cost-effective to mitigate the SEEs in analog circuits. In addition, SETs detection approaches are provided in this dissertation so that various mitigation approaches can be implemented more effectively. Performances and effectiveness of the proposed RHBD are validated through SPICE simulations on the schematic and pulsed-laser experiments on the fabricated circuits. The proposed and tested RHBD techniques can be applied to other relevant analog circuits in the industry to achieve radiation-tolerance

A 12-bit SAR ADC for a flexible tactile sensor

Successive Approximation Register (SAR) Analog-to-Digital Converters (ADC) are some of the most efficient ADC topologies available, allowing excellent performance values at low power consumption across a wide range of sampling frequencies. The proposed ADC is aimed at a tactile sensor application, requiring a low-noise and lowpower solution. In addition, it should have high SNDR to detect even the weakest signals with precision. This thesis presents a 12-bit 400 kS/s SAR ADC implemented in a 180 nm CMOS technology for such a task. The designed SAR ADC uses a hybrid R-C DAC topology consisting of a chargescaling MSB DAC and a voltage-scaling LSB DAC, allowing a good trade-off between power consumption, layout area and performance while keeping the total DAC capacitance under reasonable values. Bootstrapped switches have been implemented to preserve high-linearity during the sampling period. A double-tail dynamic comparator has been designed to obtain a low-noise measurement while ensuring suitable delay values. Finally, regarding the logic, an asynchronous implementation and the conventional switching algorithm provide a simple but effective solution to supply the digital signals of the design. Pre-layout noise simulations with input frequencies around 200 kHz show SNDR values of 72.07 dB, corresponding to an ENOB of 11.67 bits. The total power consumption is 365 ?W while the Walden and Schreier figure-of-merit (FoM) correspond to values of 275 fJ/conversion and 160 dB, respectively

Pipeline analog-to-digital converters for wide-band wireless communications

During the last decade, the development of the analog electronics has been dictated by the enormous growth of the wireless communications. Typical for the new communication standards has been an evolution towards higher data rates, which allows more services to be provided. Simultaneously, the boundary between analog and digital signal processing is moving closer to the antenna, thus aiming for a software defined radio. For analog-to-digital converters (ADCs) of radio receivers this indicates higher sample rate, wider bandwidth, higher resolution, and lower power dissipation. The radio receiver architectures, showing the greatest potential to meet the commercial trends, include the direct conversion receiver and the super heterodyne receiver with an ADC sampling at the intermediate frequency (IF). The pipelined ADC architecture, based on the switched capacitor (SC) technique, has most successfully covered the widely separated resolution and sample rate requirements of these receiver architectures. In this thesis, the requirements of ADCs in both of these receiver architectures are studied using the system specifications of the 3G WCDMA standard. From the standard and from the limited performance of the circuit building blocks, design constraints for pipeline ADCs, at the architectural and circuit level, are drawn. At the circuit level, novel topologies for all the essential blocks of the pipeline ADC have been developed. These include a dual-mode operational amplifier, low-power voltage reference circuits with buffering, and a floating-bulk bootstrapped switch for highly-linear IF-sampling. The emphasis has been on dynamic comparators: a new mismatch insensitive topology is proposed and measurement results for three different topologies are presented. At the architectural level, the optimization of the ADCs in the single-chip direct conversion receivers is discussed: the need for small area, low power, suppression of substrate noise, input and output interfaces, etc. Adaptation of the resolution and sample rate of a pipeline ADC, to be used in more flexible multi-mode receivers, is also an important topic included. A 6-bit 15.36-MS/s embedded CMOS pipeline ADC and an 8-bit 1/15.36-MS/s dual-mode CMOS pipeline ADC, optimized for low-power single-chip direct conversion receivers with single-channel reception, have been designed. The bandwidth of a pipeline ADC can be extended by employing parallelism to allow multi-channel reception. The errors resulted from mismatch of parallel signal paths are analyzed and their elimination is presented. Particularly, an optimal partitioning of the resolution between the stages, and the number of parallel channels, in time-interleaved ADCs are derived. A low-power 10-bit 200-MS/s CMOS parallel pipeline ADC employing double sampling and a front-end sample-and-hold (S/H) circuit is implemented. Emphasis of the thesis is on high-resolution pipeline ADCs with IF-sampling capability. The resolution is extended beyond the limits set by device matching by using calibration, while time interleaving is applied to widen the signal bandwidth. A review of calibration and error averaging techniques is presented. A simple digital self-calibration technique to compensate capacitor mismatch within a single-channel pipeline ADC, and the gain and offset mismatch between the channels of a time-interleaved ADC, is developed. The new calibration method is validated with two high-resolution BiCMOS prototypes, a 13-bit 50-MS/s single-channel and a 14-bit 160-MS/s parallel pipeline ADC, both utilizing a highly linear front-end allowing sampling from 200-MHz IF-band.reviewe