Automatic synthesis of analog layout : a survey

A review of recent research in the automatic synthesis of physical geometry for analog integrated circuits is presented. On introduction, an explanation of the difficulties involved in analog layout as opposed to digital layout is covered. Review of the literature then follows. Emphasis is placed on the exposition of general methods for addressing problems specific to analog layout, with the details of specific systems only being given when they surve to illustrate these methods well. The conclusion discusses problems remaining and offers a prediction as to how technology will evolve to solve them. It is argued that although progress has been and will continue to be made in the automation of analog IC layout, due to fundamental differences in the nature of analog IC design as opposed to digital design, it should not be expected that the level of automation of the former will reach that of the latter any time soon

Conservation in signal processing systems

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 205-209).Conservation principles have played a key role in the development and analysis of many existing engineering systems and algorithms. In electrical network theory for example, many of the useful theorems regarding the stability, robustness, and variational properties of circuits can be derived in terms of Tellegen's theorem, which states that a wide range of quantities, including power, are conserved. Conservation principles also lay the groundwork for a number of results related to control theory, algorithms for optimization, and efficient filter implementations, suggesting potential opportunity in developing a cohesive signal processing framework within which to view these principles. This thesis makes progress toward that goal, providing a unified treatment of a class of conservation principles that occur in signal processing systems. The main contributions in the thesis can be broadly categorized as pertaining to a mathematical formulation of a class of conservation principles, the synthesis and identification of these principles in signal processing systems, a variational interpretation of these principles, and the use of these principles in designing and gaining insight into various algorithms. In illustrating the use of the framework, examples related to linear and nonlinear signal-flow graph analysis, robust filter architectures, and algorithms for distributed control are provided.by Thomas A. Baran.Ph.D

Network-on-Chip

Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems

Layer assignment and routing optimization for advanced technologies

As VLSI technology scales to deep sub-micron and beyond, it becomes increasingly challenging to achieve timing closure for VLSI design. Since a complete design flow consists of several phases, such as logic synthesis, placement, and routing, interconnect synthesis plays an important role which includes buffer insertion/sizing and timing-driven routing. Although progress has been achieved by many advanced routing techniques, the following aspects can be exploited sufficiently for further improvement: (1) incremental layer assignment for timing optimization; (2) signal routing with the requirement of regularity; (3) power-efficient optical-electrical interconnect paradigm. Thus, to perform the layer assignment and routing optimization for advanced technologies, an automated routing engine in a global view is essential to benefit the interconnect design while satisfying specific requirements. This dissertation proposes a set of algorithms and methodology on layer assignment and routing optimization for advanced technologies. The research includes two timing-driven incremental layer assignment approaches, synergistic topology generation and routing synthesis for signal groups, and optical-electrical routing design for power efficiency. For incremental layer assignment, most of the conventional approaches target via minimization but neglect the timing issues. Meanwhile, via delays are ignored but should be considered in emerging technology nodes. Then two timing-driven incremental layer assignment frameworks are proposed, where all the nets are solved simultaneously with the integration of via delays: (1) optimization of the total sum of net delays and reduction of slew violations; (2) minimization of critical path timing in selected nets. For on-chip signal routing, the bundled bits in one group may have different pin locations, but they have to be routed in a regular manner by sharing common topologies. Very few previous works target inter-bit regularity via multi-layer topology selection. Furthermore, the routability and wire-length of the signal bits should also be optimized. Then an advanced synergistic routing engine is promoted, which is able to not only control routability and wire-length but also guide each bit routing intelligently for design regularity. For optical-electrical co-design routing, optical interconnect shows its advantage due to the dominance of bandwidth-distance-power properties. The previous works lack a detailed exploration of optical-electrical co-design for on-chip interconnects. During the transmission, signal quality can be affected by various loss sources and Electrical to Optical (EO)/Optical to Electrical (OE) conversion overheads should also be considered. Then a power-efficient routing flow for on-chip signals is presented, where optical connections can collaborate with electrical wires seamlessly. The effectiveness of proposed algorithms and techniques is demonstrated in this dissertation. These approaches are able to achieve the improvements regarding specific metrics and eventually benefit the routing flow.Electrical and Computer Engineerin

NASA JSC neural network survey results

A survey of Artificial Neural Systems in support of NASA's (Johnson Space Center) Automatic Perception for Mission Planning and Flight Control Research Program was conducted. Several of the world's leading researchers contributed papers containing their most recent results on artificial neural systems. These papers were broken into categories and descriptive accounts of the results make up a large part of this report. Also included is material on sources of information on artificial neural systems such as books, technical reports, software tools, etc

Novel Designs for Photovoltaic Arrays to Reduce Partial Shading Losses and to Ease Series Arc Fault Detection

A mismatch in a photovoltaic array implies differences in the I-V characteristics of the modules forming the array which can lead to significant energy losses known as mismatch losses. The sources of mismatch losses could be easy- or difficult-to-predict sources. This thesis proposes novel designs for photovoltaic arrays to reduce mismatch losses. The mismatch from easy-to-predict sources and its resulting losses can be reduced by altering the interconnection of the array. Therefore, this thesis proposes an optimal total-cross-tied interconnection, based on a thorough mathematical formulation, which can significantly reduce mismatch losses from easy-to-predict sources. Application examples of the operation of the optimal total-cross-tied interconnection under partial shading are presented. The effect of partial shading caused by easy- or difficult-to-predict sources can be considerably reduced by photovoltaic array reconfiguration. This thesis proposes a novel mathematical formulation for the optimal reconfiguration of photovoltaic arrays to minimize partial shading losses. The thesis formulates the reconfiguration problem as a mixed integer quadratic programming problem and finds the optimal solution using branch-and-bound algorithm. The proposed formulation can be used for equal or non-equal number of modules per row. Moreover, it can be used for fully reconfigurable or partially-reconfigurable arrays. Application examples of the operation of the reconfigurable photovoltaic array under partial shading are presented. Finally, the recently updated American National Electric Code requires the presence of a series arc fault detector in any Photovoltaic installation operating at a voltage greater than or equal to 80V. However, the Photovoltaic market nowadays lacks the presence of an accurate series arc fault detector that can detect series arc faults and discriminate between them and partial shading. The work in this thesis proposes an algorithm that can detect series arc faults and discriminate between them and partial shading in total-cross-tied arrays. This algorithm is based on the measurement of instantaneous row voltages.1 yea