40 research outputs found

    Design Methodologies and Architecture Solutions for High-Performance Interconnects

    Get PDF
    ABSTRACT In Deep Sub-Micron (DSM) technologies, interconnects play a crucial role in the correct functionality and largely impact the performance of complex System-on-Chip (SoC) designs. For technologies of 0.25µm and below, wiring capacitance dominates gate capacitance, thus rapidly increasing the interconnect-induced delay. Moreover, the coupling capacitance becomes a significant portion of the on-chip total wiring capacitance, and coupling between adjacent wires cannot be considered as a second-order effect any longer. As a consequence, the traditional top-down design methodology is ineffective, since the actual wiring delays can be computed only after layout parasitic extraction, when the physical design is completed. Fixing all the timing violations often requires several time-consuming iterations of logical and physical design, and it is essentially a trial-and-error approach. Increasingly tighter time-to-market requirements dictate that interconnect parasitics must be taken into account during all phases of the design flow, at different level of abstractions. However, given the aggressive technology scaling trends and the growing design complexity, this approach will only temporarily ameliorate the interconnect problem. We believe that in order to achieve gigascale designs in the nanometer regime, a novel design paradigm, based on new forms of regularity and newly created IP (Intellectual Property) blocks must be developed, to provide a direct path from system-level architectural exploration to physical implementation

    Analytic Delay Model of RLC Interconnects using Numerical Inversion of the Laplace Transform

    Get PDF
    Signal integrity analysis for on-chip interconnect becomes increasingly important in high-speed designs. SPICE, a conventional circuit simulator, can provide accurate prediction for interconnects, however, using SPICE is extremely computationally expensive. On the other hand, explicit moment matching technique can produce unstable poles for highly accurate approximations and implicit moment matching technique can obtain more accurate approximations at the expense of computational complexity. This thesis presents an analytic model to efficiently estimate the signal delays of RLC on-chip interconnects. It uses the numerical inversion of Laplace transform (NILT) to obtain time function, suitable for transient analysis. Since the integration formula of the NILT is numerically stable for higher order approximations, the developed algorithm provides a mechanism to increase the accuracy for delay estimation. Numerical examples are implemented and compared with HSPICE, two-pole model and Passive Reduced-Order Interconnect Macromodeling Algorithm (PRIMA) to illustrate the efficiency and validity of the proposed work

    Applications

    Get PDF

    Model Order Reduction

    Get PDF
    An increasing complexity of models used to predict real-world systems leads to the need for algorithms to replace complex models with far simpler ones, while preserving the accuracy of the predictions. This three-volume handbook covers methods as well as applications. This third volume focuses on applications in engineering, biomedical engineering, computational physics and computer science

    Advances in Bosonic Quantum Error Correction with Gottesman-Kitaev-Preskill Codes: Theory, Engineering and Applications

    Full text link
    Encoding quantum information into a set of harmonic oscillators is considered a hardware efficient approach to mitigate noise for reliable quantum information processing. Various codes have been proposed to encode a qubit into an oscillator -- including cat codes, binomial codes and Gottesman-Kitaev-Preskill (GKP) codes. These bosonic codes are among the first to reach a break-even point for quantum error correction. Furthermore, GKP states not only enable close-to-optimal quantum communication rates in bosonic channels, but also allow for error correction of an oscillator into many oscillators. This review focuses on the basic working mechanism, performance characterization, and the many applications of GKP codes, with emphasis on recent experimental progress in superconducting circuit architectures and theoretical progress in multimode GKP qubit codes and oscillators-to-oscillators (O2O) codes. We begin with a preliminary continuous-variable formalism needed for bosonic codes. We then proceed to the quantum engineering involved to physically realize GKP states. We take a deep dive into GKP stabilization and preparation in superconducting architectures and examine proposals for realizing GKP states in the optical domain (along with a concise review of GKP realization in trapped-ion platforms). Finally, we present multimode GKP qubits and GKP-O2O codes, examine code performance and discuss applications of GKP codes in quantum information processing tasks such as computing, communication, and sensing.Comment: 77+5 pages, 31 figures. Minor bugs fixed in v2. comments are welcome

    2nd Symposium on Management of Future motorway and urban Traffic Systems (MFTS 2018): Booklet of abstracts: Ispra, 11-12 June 2018

    Get PDF
    The Symposium focuses on future traffic management systems, covering the subjects of traffic control, estimation, and modelling of motorway and urban networks, with particular emphasis on the presence of advanced vehicle communication and automation technologies. As connectivity and automation are being progressively introduced in our transport and mobility systems, there is indeed a growing need to understand the implications and opportunities for an enhanced traffic management as well as to identify innovative ways and tools to optimise traffic efficiency. In particular the debate on centralised versus decentralised traffic management in the presence of connected and automated vehicles has started attracting the attention of the research community. In this context, the Symposium provides a remarkable opportunity to share novel ideas and discuss future research directions.JRC.C.4-Sustainable Transpor
    corecore