Comparison of logarithmic and floating-point number systems implemented on Xilinx Virtex-II field-programmable gate arrays

The aim of this thesis is to compare the implementation of parameterisable LNS (logarithmic number system) and floating-point high dynamic range number systems on FPGA. The Virtex/Virtex-II range of FPGAs from Xilinx, which are the most popular FPGA technology, are used to implement the designs. The study focuses on using the low level primitives of the technology in an efficient way and so initially the design issues in implementing fixed-point operators are considered. The four basic operations of addition, multiplication, division and square root are considered. Carry- free adders, ripple-carry adders, parallel multipliers and digit recurrence division and square root are discussed. The floating-point operators use the word format and exceptions as described by the IEEE std-754. A dual-path adder implementation is described in detail, as are floating-point multiplier, divider and square root components. Results and comparisons with other works are given. The efficient implementation of function evaluation methods is considered next. An overview of current FPGA methods is given and a new piecewise polynomial implementation using the Taylor series is presented and compared with other designs in the literature. In the next section the LNS word format, accuracy and exceptions are described and two new LNS addition/subtraction function approximations are described. The algorithms for performing multiplication, division and powering in the LNS domain are also described and are compared with other designs in the open literature. Parameterisable conversion algorithms to convert to/from the fixed-point domain from/to the LNS and floating-point domain are described and implementation results given. In the next chapter MATLAB bit-true software models are given that have the exact functionality as the hardware models. The interfaces of the models are given and a serial communication system to perform low speed system tests is described. A comparison of the LNS and floating-point number systems in terms of area and delay is given. Different functions implemented in LNS and floating-point arithmetic are also compared and conclusions are drawn. The results show that when the LNS is implemented with a 6-bit or less characteristic it is superior to floating-point. However, for larger characteristic lengths the floating-point system is more efficient due to the delay and exponential area increase of the LNS addition operator. The LNS is beneficial for larger characteristics than 6-bits only for specialist applications that require a high portion of division, multiplication, square root, powering operations and few additions

Hierarchical Variance Reduction Techniques for Monte Carlo Rendering

Ever since the first three-dimensional computer graphics appeared half a century ago, the goal has been to model and simulate how light interacts with materials and objects to form an image. The ultimate goal is photorealistic rendering, where the created images reach a level of accuracy that makes them indistinguishable from photographs of the real world. There are many applications ñ visualization of products and architectural designs yet to be built, special effects, computer-generated films, virtual reality, and video games, to name a few. However, the problem has proven tremendously complex; the illumination at any point is described by a recursive integral to which a closed-form solution seldom exists. Instead, computer simulation and Monte Carlo methods are commonly used to statistically estimate the result. This introduces undesirable noise, or variance, and a large body of research has been devoted to finding ways to reduce the variance. I continue along this line of research, and present several novel techniques for variance reduction in Monte Carlo rendering, as well as a few related tools. The research in this dissertation focuses on using importance sampling to pick a small set of well-distributed point samples. As the primary contribution, I have developed the first methods to explicitly draw samples from the product of distant high-frequency lighting and complex reflectance functions. By sampling the product, low noise results can be achieved using a very small number of samples, which is important to minimize the rendering times. Several different hierarchical representations are explored to allow efficient product sampling. In the first publication, the key idea is to work in a compressed wavelet basis, which allows fast evaluation of the product. Many of the initial restrictions of this technique were removed in follow-up work, allowing higher-resolution uncompressed lighting and avoiding precomputation of reflectance functions. My second main contribution is to present one of the first techniques to take the triple product of lighting, visibility and reflectance into account to further reduce the variance in Monte Carlo rendering. For this purpose, control variates are combined with importance sampling to solve the problem in a novel way. A large part of the technique also focuses on analysis and approximation of the visibility function. To further refine the above techniques, several useful tools are introduced. These include a fast, low-distortion map to represent (hemi)spherical functions, a method to create high-quality quasi-random points, and an optimizing compiler for analyzing shaders using interval arithmetic. The latter automatically extracts bounds for importance sampling of arbitrary shaders, as opposed to using a priori known reflectance functions. In summary, the work presented here takes the field of computer graphics one step further towards making photorealistic rendering practical for a wide range of uses. By introducing several novel Monte Carlo methods, more sophisticated lighting and materials can be used without increasing the computation times. The research is aimed at domain-specific solutions to the rendering problem, but I believe that much of the new theory is applicable in other parts of computer graphics, as well as in other fields

Arithmetic with the Two-Dimensional Logarithmic Number System (2DLNS)

The ever increasing demand for low power DSP applications has directed researchers to contemplate a variety of potential approaches in different contexts. Since DSP algorithms heavily rely on multiplication, there are growing demands for more efficient multiplication structures. In this regard, using some alternative number systems, which inherently are capable of reducing the hardware complexity, have been studied. The Multi-Dimensional Logarithmic Number System (MDLNS), a multi-digit and multi-base extension to the Logarithmic Number System (LNS), is considered as an alternative to the traditional binary representation for selected applications. The MDLNS provides a reduction in the size of the number representation with a non-linear mapping and promises a lower cost realization of arithmetic operations with a reduced hardware complexity. In addition, using the recursive multiplication technique, which refers to the published multiplication algorithm that uses smaller multipliers to implement a larger operation, reduces the size of operands and corresponding partial additions. As part of this research, 2DLNS-based multiplication architectures with two different levels of recursion are presented. These architectures combine some of the exibility of software with the high performance of hardware by implementing the recursive multiplication schemes on a 2DLNS processing structure. These implementations demonstrate the efciency of 2DLNS in DSP applications and show outvistanding results in terms of operation delay and dynamic power consumption. We also demonstrate the application of recursive 2DLNS multipliers to reconfigurable multiplication architectures. These architectures are able to perform single and double precision multiplication, as well as fault tolerant and dual throughput single precision operations. Modern DSP processors, such as those used in hand-held devices, may find considerable benefit from these high-performance, low-power, and high-speed recongurable architectures. In the final part of this research work, recursive 2DLNS multiplication architectures have been applied to a FIR lter structure. These implementations show considerable improvement to their binary counterparts in terms of VLSI area and power consumption

Novel arithmetic implementations using cellular neural network arrays.

The primary goal of this research is to explore the use of arrays of analog self-synchronized cells---the cellular neural network (CNN) paradigm---in the implementation of novel digital arithmetic architectures. In exploring this paradigm we also discover that the implementation of these CNN arrays produces very low system noise; that is, noise generated by the rapid switching of current through power supply die connections---so called di/dt noise. With the migration to sub 100 nanometer process technology, signal integrity is becoming a critical issue when integrating analog and digital components onto the same chip, and so the CNN architectural paradigm offers a potential solution to this problem. A typical example is the replacement of conventional digital circuitry adjacent to sensitive bio-sensors in a SoC Bio-Platform. The focus of this research is therefore to discover novel approaches to building low-noise digital arithmetic circuits using analog cellular neural networks, essentially implementing asynchronous digital logic but with the same circuit components as used in analog circuit design. We address our exploration by first improving upon previous research into CNN binary arithmetic arrays. The second phase of our research introduces a logical extension of the binary arithmetic method to implement binary signed-digit (BSD) arithmetic. To this end, a new class of CNNs that has three stable states is introduced, and is used to implement arithmetic circuits that use binary inputs and outputs but internally uses the BSD number representation. Finally, we develop CNN arrays for a 2-dimensional number representation (the Double-base Number System - DBNS). A novel adder architecture is described in detail, that performs the addition as well as reducing the representation for further processing; the design incorporates an innovative self-programmable array. Extensive simulations have shown that our new architectures can reduce system noise by almost 70dB and crosstalk by more than 23dB over standard digital implementations.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2005 .I27. Source: Dissertation Abstracts International, Volume: 66-11, Section: B, page: 6159. Thesis (Ph.D.)--University of Windsor (Canada), 2005

WiFi-Based Human Activity Recognition Using Attention-Based BiLSTM

Recently, significant efforts have been made to explore human activity recognition (HAR) techniques that use information gathered by existing indoor wireless infrastructures through WiFi signals without demanding the monitored subject to carry a dedicated device. The key intuition is that different activities introduce different multi-paths in WiFi signals and generate different patterns in the time series of channel state information (CSI). In this paper, we propose and evaluate a full pipeline for a CSI-based human activity recognition framework for 12 activities in three different spatial environments using two deep learning models: ABiLSTM and CNN-ABiLSTM. Evaluation experiments have demonstrated that the proposed models outperform state-of-the-art models. Also, the experiments show that the proposed models can be applied to other environments with different configurations, albeit with some caveats. The proposed ABiLSTM model achieves an overall accuracy of 94.03%, 91.96%, and 92.59% across the 3 target environments. While the proposed CNN-ABiLSTM model reaches an accuracy of 98.54%, 94.25% and 95.09% across those same environments

Strategies for neural networks in ballistocardiography with a view towards hardware implementation

A thesis submitted for the degree of Doctor of Philosophy at the University of LutonThe work described in this thesis is based on the results of a clinical trial conducted by the research team at the Medical Informatics Unit of the University of Cambridge, which show that the Ballistocardiogram (BCG) has prognostic value in detecting impaired left ventricular function before it becomes clinically overt as myocardial infarction leading to sudden death. The objective of this study is to develop and demonstrate a framework for realising an on-line BCG signal classification model in a portable device that would have the potential to find pathological signs as early as possible for home health care. Two new on-line automatic BeG classification models for time domain BeG classification are proposed. Both systems are based on a two stage process: input feature extraction followed by a neural classifier. One system uses a principal component analysis neural network, and the other a discrete wavelet transform, to reduce the input dimensionality. Results of the classification, dimensionality reduction, and comparison are presented. It is indicated that the combined wavelet transform and MLP system has a more reliable performance than the combined neural networks system, in situations where the data available to determine the network parameters is limited. Moreover, the wavelet transfonn requires no prior knowledge of the statistical distribution of data samples and the computation complexity and training time are reduced. Overall, a methodology for realising an automatic BeG classification system for a portable instrument is presented. A fully paralJel neural network design for a low cost platform using field programmable gate arrays (Xilinx's XC4000 series) is explored. This addresses the potential speed requirements in the biomedical signal processing field. It also demonstrates a flexible hardware design approach so that an instrument's parameters can be updated as data expands with time. To reduce the hardware design complexity and to increase the system performance, a hybrid learning algorithm using random optimisation and the backpropagation rule is developed to achieve an efficient weight update mechanism in low weight precision learning. The simulation results show that the hybrid learning algorithm is effective in solving the network paralysis problem and the convergence is much faster than by the standard backpropagation rule. The hidden and output layer nodes have been mapped on Xilinx FPGAs with automatic placement and routing tools. The static time analysis results suggests that the proposed network implementation could generate 2.7 billion connections per second performance

NASA Tech Briefs, November 1993

Topics covered: Advanced Manufacturing; Electronic Components and Circuits; Electronic Systems; Physical Sciences; Materials; Computer Programs; Mechanics; Machinery; Fabrication Technology; Mathematics and Information Sciences; Life Sciences

Collective Communications and Computation Mechanisms on the RF Channel for Organic Printed Smart Labels and Resource-limited IoT Nodes

Radio Frequency IDentification (RFID) and Wireless Sensor Networks (WSN) are seen as enabler technologies for realizing the Internet of Things (IoT). Organic and printed Electronics (OE) has the potential to provide low cost and all-printable smart RFID labels in high volumes. With regard to WSN, power harvesting techniques and resource-efficient communications are promising key technologies to create sustainable and for the environment friendly sensing devices. However, the implementation of OE smart labels is only allowing printable devices of ultra-low hardware complexity, that cannot employ standard RFID communications. And, the deployment of current WSN technology is far away from offering battery-free and low-cost sensing technology. To this end, the steady growth of IoT is increasing the demand for more network capacity and computational power. With respect to wireless communications research, the state-of-the-art employs superimposed radio transmission in form of physical layer network coding and computation over the MAC to increase information flow and computational power, but lacks on practicability and robustness so far. With regard to these research challenges we developed in particular two approaches, i.e., code-based Collective Communications for dense sensing environments, and time-based Collective Communications (CC) for resource-limited WSNs. In respect to the code-based CC approach we exploit the principle of superimposed radio transmission to acquire highly scalable and robust communications obtaining with it at the same time as well minimalistic smart RFID labels, that can be manufactured in high volume with present-day OE. The implementation of our code-based CC relies on collaborative and simultaneous transmission of randomly drawn burst sequences encoding the data. Based on the framework of hyper-dimensional computing, statistical laws and the superposition principle of radio waves we obtained the communication of so called ensemble information, meaning the concurrent bulk reading of sensed values, ranges, quality rating, identifiers (IDs), and so on. With 21 transducers on a small-scale reader platform we tested the performance of our approach successfully proving the scalability and reliability. To this end, we implemented our code-based CC mechanism into an all-printable passive RFID label down to the logic gate level, indicating a circuit complexity of about 500 transistors. In respect to time-based CC approach we utilize the superimposed radio transmission to obtain resource-limited WSNs, that can be deployed in wide areas for establishing, e.g., smart environments. In our application scenario for resource-limited WSN, we utilize the superimposed radio transmission to calculate functions of interest, i.e., to accomplish data processing directly on the radio channel. To prove our concept in a case study, we created a WSN with 15 simple nodes measuring the environmental mean temperature. Based on our analysis about the wireless computation error we were able to minimize the stochastic error arbitrarily, and to remove the systematic error completely

A microcomputer controller for a nylon spinning machine

This thesis will show how a new type of controller for a Nylon spinning machine was developed from an initial specification. The controller is a component in a loosely coupled feedback system which reads two tachometer pulse trains and various plant interlocks and produces two pulse trains which are used to control two solid state variable frequency variable voltage inverters and their AC motors. The specification calls for 24 controllers to be linked to a PDP 11/23 host computer which holds a library of operating parameters which can be downloaded into each control unit by ~n operator. After examining the requirements of the system, a microcomputer implementation was chosen as· best meeting the needs of the project. Elsewhere in the plant several earlier attempts at using micro-computers as dedicated controllers had been made, with rather poor results. Consideration of the future requirements of the company showed that there was a clear role for these controllers, and it was clear that there was a need to define standards for their development and implementation, and so a survey of the company's requirements was done, on the basis of which a standard was adopted. The thesis covers ali system related aspects of the project, from the initial selection of a microcomputer system and software development system to the design and implementation of the controller

Online learning of physics during a pandemic: A report from an academic experience in Italy

The arrival of the Sars-Cov II has opened a new window on teaching physics in academia. Frontal lectures have left space for online teaching, teachers have been faced with a new way of spreading knowledge, adapting contents and modalities of their courses. Students have faced up with a new way of learning physics, which relies on free access to materials and their informatics knowledge. We decided to investigate how online didactics has influenced students’ assessments, motivation, and satisfaction in learning physics during the pandemic in 2020. The research has involved bachelor (n = 53) and master (n = 27) students of the Physics Department at the University of Cagliari (N = 80, 47 male; 33 female). The MANOVA supported significant mean differences about gender and university level with higher values for girls and master students in almost all variables investigated. The path analysis showed that student-student, student-teacher interaction, and the organization of the courses significantly influenced satisfaction and motivation in learning physics. The results of this study can be used to improve the standards of teaching in physics at the University of Cagliar