A Practical Version of Lee\u27s Multicast Switch Architecture

This paper describes several improvements to Lee\u27s multicast switch architecture. Our improvements make Lee\u27s architecture practical, allowing it to achieve maximum network throughput under worst-case conditions and drastically reducing the amount of memory required for addressing of multicast cells. These improvements allow multicast to be added to a 256 port switch with 150 Mb/s links at a cost of about two additional chips per port

On-board B-ISDN fast packet switching architectures. Phase 2: Development. Proof-of-concept architecture definition report

For the next-generation packet switched communications satellite system with onboard processing and spot-beam operation, a reliable onboard fast packet switch is essential to route packets from different uplink beams to different downlink beams. The rapid emergence of point-to-point services such as video distribution, and the large demand for video conference, distributed data processing, and network management makes the multicast function essential to a fast packet switch (FPS). The satellite's inherent broadcast features gives the satellite network an advantage over the terrestrial network in providing multicast services. This report evaluates alternate multicast FPS architectures for onboard baseband switching applications and selects a candidate for subsequent breadboard development. Architecture evaluation and selection will be based on the study performed in phase 1, 'Onboard B-ISDN Fast Packet Switching Architectures', and other switch architectures which have become commercially available as large scale integration (LSI) devices

Design and analysis of a scalable terabit multicast packet switch : architecture and scheduling algorithms

Internet growth and success not only open a primary route of information exchange for millions of people around the world, but also create unprecedented demand for core network capacity. Existing switches/routers, due to the bottleneck from either switch architecture or arbitration complexity, can reach a capacity on the order of gigabits per second, but few of them are scalable to large capacity of terabits per second. In this dissertation, we propose three novel switch architectures with cooperated scheduling algorithms to design a terabit backbone switch/router which is able to deliver large capacity, multicasting, and high performance along with Quality of Service (QoS). Our switch designs benefit from unique features of modular switch architecture and distributed resource allocation scheme. Switch I is a unique and modular design characterized by input and output link sharing. Link sharing resolves output contention and eliminates speedup requirement for central switch fabric. Hence, the switch architecture is scalable to any large size. We propose a distributed round robin (RR) scheduling algorithm which provides fairness and has very low arbitration complexity. Switch I can achieve good performance under uniform traffic. However, Switch I does not perform well for non-uniform traffic. Switch II, as a modified switch design, employs link sharing as well as a token ring to pursue a solution to overcome the drawback of Switch 1. We propose a round robin prioritized link reservation (RR+POLR) algorithm which results in an improved performance especially under non-uniform traffic. However, RR+POLR algorithm is not flexible enough to adapt to the input traffic. In Switch II, the link reservation rate has a great impact on switch performance. Finally, Switch III is proposed as an enhanced switch design using link sharing and dual round robin rings. Packet forwarding is based on link reservation. We propose a queue occupancy based dynamic link reservation (QOBDLR) algorithm which can adapt to the input traffic to provide a fast and fair link resource allocation. QOBDLR algorithm is a distributed resource allocation scheme in the sense that dynamic link reservation is carried out according to local available information. Arbitration complexity is very low. Compared to the output queued (OQ) switch which is known to offer the best performance under any traffic pattern, Switch III not only achieves performance as good as the OQ switch, but also overcomes speedup problem which seriously limits the OQ switch to be a scalable switch design. Hence, Switch III would be a good choice for high performance, scalable, large-capacity core switches

On-board B-ISDN fast packet switching architectures. Phase 1: Study

The broadband integrate services digital network (B-ISDN) is an emerging telecommunications technology that will meet most of the telecommunications networking needs in the mid-1990's to early next century. The satellite-based system is well positioned for providing B-ISDN service with its inherent capabilities of point-to-multipoint and broadcast transmission, virtually unlimited connectivity between any two points within a beam coverage, short deployment time of communications facility, flexible and dynamic reallocation of space segment capacity, and distance insensitive cost. On-board processing satellites, particularly in a multiple spot beam environment, will provide enhanced connectivity, better performance, optimized access and transmission link design, and lower user service cost. The following are described: the user and network aspects of broadband services; the current development status in broadband services; various satellite network architectures including system design issues; and various fast packet switch architectures and their detail designs

Novel techniques in large scaleable ATM switches

Bibliography: p. 172-178.This dissertation explores the research area of large scale ATM switches. The requirements for an ATM switch are determined by overviewing the ATM network architecture. These requirements lead to the discussion of an abstract ATM switch which illustrates the components of an ATM switch that automatically scale with increasing switch size (the Input Modules and Output Modules) and those that do not (the Connection Admission Control and Switch Management systems as well as the Cell Switch Fabric). An architecture is suggested which may result in a scalable Switch Management and Connection Admission Control function. However, the main thrust of the dissertation is confined to the cell switch fabric. The fundamental mathematical limits of ATM switches and buffer placement is presented next emphasising the desirability of output buffering. This is followed by an overview of the possible routing strategies in a multi-stage interconnection network. A variety of space division switches are then considered which leads to a discussion of the hypercube fabric, (a novel switching technique). The hypercube fabric achieves good performance with an O(N.log₂N)²) scaling. The output module, resequencing, cell scheduling and output buffering technique is presented leading to a complete description of the proposed ATM switch. Various traffic models are used to quantify the switch's performance. These include a simple exponential inter-arrival time model, a locality of reference model and a self-similar, bursty, multiplexed Variable Bit Rate (VBR) model. FIFO queueing is simple to implement in an ATNI switch, however, more responsive queueing strategies can result in an improved performance. An associative memory is presented which allows the separate queues in the ATM switch to be effectively logically combined into a single FIFO queue. The associative memory is described in detail and its feasibility is shown by laying out the Integrated Circuit masks and performing an analogue simulation of the IC's performance is SPICE3. Although optimisations were required to the original design, the feasibility of the approach is shown with a 15Ƞs write time and a 160Ƞs read time for a 32 row, 8 priority bit, 10 routing bit version of the memory. This is achieved with 2µm technology, more advanced technologies may result in even better performance. The various traffic models and switch models are simulated in a number of runs. This shows the performance of the hypercube which outperforms a Clos network of equivalent technology and approaches the performance of an ideal reference fabric. The associative memory leverages a significant performance advantage in the hypercube network and a modest advantage in the Clos network. The performance of the switches is shown to degrade with increasing traffic density, increasing locality of reference, increasing variance in the cell rate and increasing burst length. Interestingly, the fabrics show no real degradation in response to increasing self similarity in the fabric. Lastly, the appendices present suggestions on how redundancy, reliability and multicasting can be achieved in the hypercube fabric. An overview of integrated circuits is provided. A brief description of commercial ATM switching products is given. Lastly, a road map to the simulation code is provided in the form of descriptions of the functionality found in all of the files within the source tree. This is intended to provide the starting ground for anyone wishing to modify or extend the simulation system developed for this thesis

Switching techniques for broadband ISDN

The properties of switching techniques suitable for use in broadband networks have been investigated. Methods for evaluating the performance of such switches have been reviewed. A notation has been introduced to describe a class of binary self-routing networks. Hence a technique has been developed for determining the nature of the equivalence between two networks drawn from this class. The necessary and sufficient condition for two packets not to collide in a binary self-routing network has been obtained. This has been used to prove the non-blocking property of the Batcher-banyan switch. A condition for a three-stage network with channel grouping and link speed-up to be nonblocking has been obtained, of which previous conditions are special cases. A new three-stage switch architecture has been proposed, based upon a novel cell-level algorithm for path allocation in the intermediate stage of the switch. The algorithm is suited to hardware implementation using parallelism to achieve a very short execution time. An array of processors is required to implement the algorithm The processor has been shown to be of simple design. It must be initialised with a count representing the number of cells requesting a given output module. A fast method has been described for performing the request counting using a non-blocking binary self-routing network. Hardware is also required to forward routing tags from the processors to the appropriate data cells, when they have been allocated a path through the intermediate stage. A method of distributing these routing tags by means of a non-blocking copy network has been presented. The performance of the new path allocation algorithm has been determined by simulation. The rate of cell loss can increase substantially in a three-stage switch when the output modules are non-uniformly loaded. It has been shown that the appropriate use of channel grouping in the intermediate stage of the switch can reduce the effect of non-uniform loading on performance

Agent organization in the KP

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (p. 181-191).In designing and building a network like the Internet, we continue to face the problems of scale and distribution. With the dramatic expansion in scale and heterogeneity of the Internet, network management has become an increasingly difficult task. Furthermore, network applications often need to maintain efficient organization among the participants by collecting information from the underlying networks. Such individual information collection activities lead to duplicate efforts and contention for network resources. The Knowledge Plane (KP) is a new common construct that provides knowledge and expertise to meet the functional, policy and scaling requirements of network management, as well as to create synergy and exploit commonality among many network applications. To achieve these goals, we face many challenging problems, including widely distributed data collection, efficient processing of that data, wide availability of the expertise, etc. In this thesis, to provide better support for network management and large-scale network applications, I propose a knowledge plane architecture that consists of a network knowledge plane (NetKP) at the network layer, and on top of it, multiple specialized KPs (spec-KPs). The NetKP organizes agents to provide valuable knowledge and facilities about the Internet to the spec-KPs. Each spec-KP is specialized in its own area of interest. In both the NetKP and the spec-KPs, agents are organized into regions based on different sets of constraints. I focus on two key design issues in the NetKP: (1) a region-based architecture for agent organization, in which I design an efficient and non-intrusive organization among regions that combines network topology and a distributed hash table; (2) request and knowledge dissemination, in which I design a robust and efficient broadcast and aggregation mechanism using a tree structure among regions.(cont.) In the spec-KPs, I build two examples: experiment management on the PlanetLab testbed and distributed intrusion detection on the DETER testbed. The experiment results suggest a common approach driven by the design principles of the Internet and more specialized constraints can derive productive organization for network management and applications.by Ji Li.Ph.D

A server-less architecture for building scalable, reliable, and cost-effective video-on-demand systems.

Leung Wai Tak.Thesis (M.Phil.)--Chinese University of Hong Kong, 2002.Includes bibliographical references (leaves 58-60).Abstracts in English and Chinese.Acknowledgement --- p.IAbstract --- p.II摘要 --- p.IIIChapter Chapter 1 --- Introduction --- p.1Chapter Chapter 2 --- Related Works --- p.5Chapter 2.1 --- Previous Works --- p.5Chapter 2.2 --- Contributions of this Study --- p.7Chapter Chapter 3 --- Architecture --- p.9Chapter 3.1 --- Data Placement Policy --- p.10Chapter 3.2 --- Retrieval and Transmission Scheduling --- p.13Chapter 3.3 --- Fault Tolerance --- p.20Chapter Chapter 4 --- Performance Modeling --- p.22Chapter 4.1 --- Storage Requirement --- p.22Chapter 4.2 --- Network Bandwidth Requirement --- p.23Chapter 4.3 --- Buffer Requirement --- p.24Chapter 4.4 --- System Response Time --- p.27Chapter Chapter 5 --- System Reliability --- p.29Chapter 5.1 --- System Failure Model --- p.29Chapter 5.2 --- Minimum System Repair Capability --- p.32Chapter 5.3 --- Redundancy Configuration --- p.35Chapter Chapter 6 --- System Dimensioning --- p.37Chapter 6.1 --- Storage Capacity --- p.38Chapter 6.2 --- Network Capacity --- p.38Chapter 6.3 --- Disk Access Bandwidth --- p.39Chapter 6.4 --- Buffer Requirement --- p.41Chapter 6.5 --- System Response Time --- p.43Chapter Chapter 7 --- Multiple Parity Groups --- p.45Chapter 7.1 --- System Failure Model --- p.47Chapter 7.2 --- Buffer Requirement --- p.47Chapter 7.3 --- System Response Time --- p.49Chapter 7.4 --- Redundancy Configuration --- p.49Chapter 7.5 --- Scalability --- p.51Chapter Chapter 8 --- Conclusions and Future Works --- p.53Appendix --- p.55Chapter A. --- Derivation of the Artificial Admission Delay --- p.55Chapter B. --- Derivation of the Receiver Buffer Requirement --- p.56Bibliography --- p.5

Physical and Link Layer Implications in Vehicle Ad Hoc Networks

Vehicle Ad hoc Networks (V ANET) have been proposed to provide safety on the road and deliver road traffic information and route guidance to drivers along with commercial applications. However the challenges facing V ANET are numerous. Nodes move at high speeds, road side units and basestations are scarce, the topology is constrained by the road geometry and changes rapidly, and the number of nodes peaks suddenly in traffic jams. In this thesis we investigate the physical and link layers of V ANET and propose methods to achieve high data rates and high throughput. For the physical layer, we examine the use of Vertical BLAST (VB LAST) systems as they provide higher capacities than single antenna systems in rich fading environments. To study the applicability of VB LAST to VANET, a channel model was developed and verified using measurement data available in the literature. For no to medium line of sight, VBLAST systems provide high data rates. However the performance drops as the line of sight strength increases due to the correlation between the antennas. Moreover, the performance of VBLAST with training based channel estimation drops as the speed increases since the channel response changes rapidly. To update the channel state information matrix at the receiver, a channel tracking algorithm for flat fading channels was developed. The algorithm updates the channel matrix thus reducing the mean square error of the estimation and improving the bit error rate (BER). The analysis of VBLAST-OFDM systems showed they experience an error floor due to inter-carrier interference (lCI) which increases with speed, number of antennas transmitting and number of subcarriers used. The update algorithm was extended to VBLAST -OFDM systems and it showed improvements in BER performance but still experienced an error floor. An algorithm to equalise the ICI contribution of adjacent subcarriers was then developed and evaluated. The ICI equalisation algorithm reduces the error floor in BER as more subcarriers are equalised at the expense of more hardware complexity. The connectivity of V ANET was investigated and it was found that for single lane roads, car densities of 7 cars per communication range are sufficient to achieve high connectivity within the city whereas 12 cars per communication range are required for highways. Multilane roads require higher densities since cars tend to cluster in groups. Junctions and turns have lower connectivity than straight roads due to disconnections at the turns. Although higher densities improve the connectivity and, hence, the performance of the network layer, it leads to poor performance at the link layer. The IEEE 802.11 p MAC layer standard under development for V ANET uses a variant of Carrier Sense Multiple Access (CSMA). 802.11 protocols were analysed mathematically and via simulations and the results prove the saturation throughput of the basic access method drops as the number of nodes increases thus yielding very low throughput in congested areas. RTS/CTS access provides higher throughput but it applies only to unicast transmissions. To overcome the limitations of 802.11 protocols, we designed a protocol known as SOFT MAC which combines Space, Orthogonal Frequency and Time multiple access techniques. In SOFT MAC the road is divided into cells and each cell is allocated a unique group of subcarriers. Within a cell, nodes share the available subcarriers using a combination of TDMA and CSMA. The throughput analysis of SOFT MAC showed it has superior throughput compared to the basic access and similar to the RTS/CTS access of 802.11