A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.A fully-integrated reconfigurable dual-band (760-960 MHz and 2.4-2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA's operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by x3.24 and x1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by x2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.Peer reviewe

Design Considerations of a Sub-50 {\mu}W Receiver Front-end for Implantable Devices in MedRadio Band

Emerging health-monitor applications, such as information transmission through multi-channel neural implants, image and video communication from inside the body etc., calls for ultra-low active power (<50${\mu}$W) high data-rate, energy-scalable, highly energy-efficient (pJ/bit) radios. Previous literature has strongly focused on low average power duty-cycled radios or low power but low-date radios. In this paper, we investigate power performance trade-off of each front-end component in a conventional radio including active matching, down-conversion and RF/IF amplification and prioritize them based on highest performance/energy metric. The analysis reveals 50${\Omega}$ active matching and RF gain is prohibitive for 50${\mu}$W power-budget. A mixer-first architecture with an N-path mixer and a self-biased inverter based baseband LNA, designed in TSMC 65nm technology show that sub 50${\mu}$W performance can be achieved up to 10Mbps (< 5pJ/b) with OOK modulation.Comment: Accepted to appear on International Conference on VLSI Design 2018 (VLSID

Ultra Small Antenna and Low Power Receiver for Smart Dust Wireless Sensor Networks

Wireless Sensor Networks have the potential for profound impact on our daily lives. Smart Dust Wireless Sensor Networks (SDWSNs) are emerging members of the Wireless Sensor Network family with strict requirements on communication node sizes (1 cubic centimeter) and power consumption (< 2mW during short on-states). In addition, the large number of communication nodes needed in SDWSN require highly integrated solutions. This dissertation develops new design techniques for low-volume antennas and low-power receivers for SDWSN applications. In addition, it devises an antenna and low noise amplifier co-design methodology to increase the level of design integration, reduce receiver noise, and reduce the development cycle. This dissertation first establishes stringent principles for designing SDWSN electrically small antennas (ESAs). Based on these principles, a new ESA, the F-Inverted Compact Antenna (FICA), is designed at 916MHz. This FICA has a significant advantage in that it uses a small-size ground plane. The volume of this FICA (including the ground plane) is only 7% of other state-of-the-art ESAs, while its efficiency (48.53%) and gain (-1.38dBi) are comparable to antennas of much larger dimensions. A physics-based circuit model is developed for this FICA to assist system level design at the earliest stage, including optimization of the antenna performance. An antenna and low noise amplifier (LNA) co-design method is proposed and proven to be valid to design low power LNAs with the very low noise figure of only 1.5dB. To reduce receiver power consumption, this dissertation proposes a novel LNA active device and an input/ouput passive matching network optimization method. With this method, a power efficient high voltage gain cascode LNA was designed in a 0.13um CMOS process with only low quality factor inductors. This LNA has a 3.6dB noise figure, voltage gain of 24dB, input third intercept point (IIP3) of 3dBm, and power consumption of 1.5mW at 1.0V supply voltage. Its figure of merit, using the typical definition, is twice that of the best in the literature. A full low power receiver is developed with a sensitivity of -58dBm, chip area of 1.1mm2, and power consumption of 2.85mW

Improving practical sensitivity of energy optimized wake-up receivers: proof of concept in 65nm CMOS

We present a high performance low-power digital base-band architecture, specially designed for an energy optimized duty-cycled wake-up receiver scheme. Based on a careful wake-up beacon design, a structured wake-up beacon detection technique leads to an architecture that compensates for the implementation loss of a low-power wake-up receiver front-end at low energy and area costs. Design parameters are selected by energy optimization and the architecture is easily scalable to support various network sizes. Fabricated in 65nm CMOS, the digital base-band consumes 0.9uW (V_DD=0.37V) in sub-threshold operation at 250kbps, with appropriate 97% wake-up beacon detection and 0.04% false alarm probabilities. The circuit is fully functional at a minimum V_DD of 0.23V at f_max=5kHz and 0.018uW power consumption. Based on these results we show that our digital base-band can be used as a companion to compensate for front-end implementation losses resulting from the limited wake-up receiver power budget at a negligible cost. This implies an improvement of the practical sensitivity of the wake-up receiver, compared to what is traditionally reported.Comment: Submitted to IEEE Sensors Journa

Comparing Analog Front-Ends for Duty-Cycled Wake-Up Receivers in Wireless Sensor Networks

Using ultralow-power wake-up receivers (WRxs) can reduce idle listening energy cost in wireless sensor networks with low traffic intensity. This has led to many WRx analog front-end (AFE) designs presented in literature, with a large variety of trade-offs between the sensitivity, the data rate, and the power consumption. Energy consumed during wake-up in a network depends on many parameters and without a unified energy analysis, we cannot compare performance of different AFEs. We present an analysis of duty-cycled WRx schemes which provides a simple tool for such a comparison based on the energy consumed in an entire single-hop network during a wake-up. The simplicity is largely due to the fact that all network and communication parameter settings can be condensed into a single scenario constant. This tool allows us to both compare AFEs for specific scenarios and draw more general conclusions about AFE performance across all scenarios

Multi-channel 180pJ/b 2.4GHz FBAR-based receiver

A three-channel 2.4GHz OOK receiver is designed in 65nm CMOS and leverages MEMS to enable multiple sub-channels of operation within a band at a very low energy per received bit. The receive chain features an LNA/mixer architecture that efficiently multiplexes signal pathways without degrading the quality factor of the resonators. The single-balanced mixer and ultra-low power ring oscillator convert the signal to IF, where it is efficiently amplified to enable envelope detection. The receiver consumes a total of 180pJ/b from a 0.7V supply while achieving a BER=10-3 sensitivity of -67dBm at a 1Mb/s data rate.Semiconductor Research Corporation. Interconnect Focus CenterNatural Sciences and Engineering Research Council of Canada (Fellowship

Wireless body sensor networks for health-monitoring applications

This is an author-created, un-copyedited version of an article accepted for publication in Physiological Measurement. The publisher is not responsible for any errors or omissions in this version of the manuscript or any version derived from it. The Version of Record is available online at http://dx.doi.org/10.1088/0967-3334/29/11/R01

A Sub-nW 2.4 GHz Transmitter for Low Data-Rate Sensing Applications

This paper presents the design of a narrowband transmitter and antenna system that achieves an average power consumption of 78 pW when operating at a duty-cycled data rate of 1 bps. Fabricated in a 0.18 μm CMOS process, the transmitter employs a direct-RF power oscillator topology where a loop antenna acts as a both a radiative and resonant element. The low-complexity single-stage architecture, in combination with aggressive power gating techniques and sizing optimizations, limited the standby power of the transmitter to only 39.7 pW at 0.8 V. Supporting both OOK and FSK modulations at 2.4 GHz, the transmitter consumed as low as 38 pJ/bit at an active-mode data rate of 5 Mbps. The loop antenna and integrated diodes were also used as part of a wireless power transfer receiver in order to kick-start the system power supply prior to energy harvesting operation.Semiconductor Research Corporation. Interconnect Focus CenterSemiconductor Research Corporation. C2S2 Focus CenterNational Institutes of Health (U.S.) (Grant K08 DC010419)National Institutes of Health (U.S.) (Grant T32 DC00038)Bertarelli Foundatio

High-performance wireless power and data transfer interface for implantable medical devices

D’importants progès ont été réalisés dans le développement des systèmes biomédicaux implantables grâce aux dernières avancées de la microélectronique et des technologies sans fil. Néanmoins, ces appareils restent difficiles à commercialier. Cette situation est due particulièrement à un manque de stratégies de design capable supporter les fonctionnalités exigées, aux limites de miniaturisation, ainsi qu’au manque d’interface sans fil à haut débit fiable et faible puissance capable de connecter les implants et les périphériques externes. Le nombre de sites de stimulation et/ou d’électrodes d’enregistrement retrouvés dans les dernières interfaces cerveau-ordinateur (IMC) ne cesse de croître afin d’augmenter la précision de contrôle, et d’améliorer notre compréhension des fonctions cérébrales. Ce nombre est appelé à atteindre un millier de site à court terme, ce qui exige des débits de données atteingnant facilement les 500 Mbps. Ceci étant dit, ces travaux visent à élaborer de nouvelles stratégies innovantes de conception de dispositifs biomédicaux implantables afin de repousser les limites mentionnées ci-dessus. On présente de nouvelles techniques faible puissance beaucoup plus performantes pour le transfert d’énergie et de données sans fil à haut débit ainsi que l’analyse et la réalisation de ces dernières grâce à des prototypes microélectroniques CMOS. Dans un premier temps, ces travaux exposent notre nouvelle structure multibobine inductive à résonance présentant une puissance sans fil distribuée uniformément pour alimenter des systèmes miniatures d’étude du cerveaux avec des models animaux en ilberté ainsi que des dispositifs médicaux implantbles sans fil qui se caractérisent par une capacité de positionnement libre. La structure propose un lien de résonance multibobines inductive, dont le résonateur principal est constitué d’une multitude de résonateurs identiques disposés dans une matrice de bobines carrées. Ces dernières sont connectées en parallèle afin de réaliser des surfaces de puissance (2D) ainsi qu’une chambre d’alimentation (3D). La chambre proposée utilise deux matrices de résonateurs de base, mises face à face et connectés en parallèle afin d’obtenir une distribution d’énergie uniforme en 3D. Chaque surface comprend neuf bobines superposées, connectées en parallèle et réailsées sur une carte de circuit imprimé deux couches FR4. La chambre dispose d’un mécanisme naturel de localisation de puissance qui facilite sa mise en oeuvre et son fonctionnement. En procédant ainsi, nous évitons la nécessité d’une détection active de l’emplacement de la charge et le contrôle d’alimentation. Notre approche permet à cette surface d’alimentation unique de fournir une efficacité de transfert de puissance (PTE) de 69% et une puissance délivrée à la charge (PDL) de 120 mW, pour une distance de séparation de 4 cm, tandis que le prototype de chambre complet fournit un PTE uniforme de 59% et un PDL de 100 mW en 3D, partout à l’intérieur de la chambre avec un volume de chambre de 27 × 27 × 16 cm3. Une étape critique avant d’utiliser un dispositif implantable chez les humains consiste à vérifier ses fonctionnalités sur des sujets animaux. Par conséquent, la chambre d’énergie sans fil conçue sera utilisée afin de caractériser les performances d’ une interface sans fil de transmisison de données dans un environnement réaliste in vivo avec positionement libre. Un émetteur-récepteur full-duplex (FDT) entièrement intégré qui se caractérise par sa faible puissance est conçu pour réaliser une interfaces bi-directionnelles (stimulation et enregistrement) avec des débits asymétriques: des taux de tramnsmission plus élevés sont nécessaires pour l’enregistrement électrophysiologique multicanal (signaux de liaison montante) alors que les taux moins élevés sont utilisés pour la stimulation (les signaux de liaison descendante). L’émetteur (TX) et le récepteur (RX) se partagent une seule antenne afin de réduire la taille de l’implant. L’émetteur utilise la radio ultra-large bande par impulsions (IR-UWB) basée sur l’approche edge combining et le RX utilise la bande ISM (Industrielle, Scientifique et Médicale) de fréquence central 2.4 GHz et la modulation on-off-keying (OOK). Une bonne isolation (&gt; 20 dB) est obtenue entre le TX et le RX grâce à 1) la mise en forme les impulsions émises dans le spectre UWB non réglementée (3.1-7 GHz), et 2) le filtrage espace-efficace (évitant l’utilisation d’un circulateur ou d’un diplexeur) du spectre du lien de communication descendant directement au niveau de l’ amplificateur à faible bruit (LNA). L’émetteur UWB 3.1-7 GHz utilise un e modultion OOK ainsi qu’une modulation par déplacement de phase (BPSK) à seulement 10.8 pJ / bits. Le FDT proposé permet d’atteindre 500 Mbps de débit de données en lien montant et 100 Mbps de débit de données de lien descendant. Il est entièrement intégré dans un procédé TSMC CMOS 0.18 um standard et possède une taille totale de 0.8 mm2. La consommation totale d’énergie mesurée est de 10.4 mW (5 mW pour RX et 5.4 mW pour TX au taux de 500 Mbps).In recent years, there has been major progress on implantable biomedical systems that support most of the functionalities of wireless implantable devices. Nevertheless, these devices remain mostly restricted to be commercialized, in part due to weakness of a straightforward design to support the required functionalities, limitation on miniaturization, and lack of a reliable low-power high data rate interface between implants and external devices. This research provides novel strategies on the design of implantable biomedical devices that addresses these limitations by presenting analysis and techniques for wireless power transfer and efficient data transfer. The first part of this research includes our proposed novel resonance-based multicoil inductive power link structure with uniform power distribution to wirelessly power up smart animal research systems and implanted medical devices with high power efficiency and free positioning capability. The proposed structure consists of a multicoil resonance inductive link, which primary resonator array is made of several identical resonators enclosed in a scalable array of overlapping square coils that are connected in parallel and arranged in power surface (2D) and power chamber (3D) configurations. The proposed chamber uses two arrays of primary resonators, facing each other, and connected in parallel to achieve uniform power distribution in 3D. Each surface includes 9 overlapped coils connected in parallel and implemented into two layers of FR4 printed circuit board. The chamber features a natural power localization mechanism, which simplifies its implementation and eases its operation by avoiding the need for active detection of the load location and power control mechanisms. A single power surface based on the proposed approach can provide a power transfer efficiency (PTE) of 69% and a power delivered to the load (PDL) of 120 mW, for a separation distance of 4 cm, whereas the complete chamber prototype provides a uniform PTE of 59% and a PDL of 100 mW in 3D, everywhere inside the chamber with a chamber size of 27×27×16 cm3. The second part of this research includes our proposed novel, fully-integrated, low-power fullduplex transceiver (FDT) to support bi-directional neural interfacing applications (stimulating and recording) with asymmetric data rates: higher rates are required for recording (uplink signals) than stimulation (downlink signals). The transmitter (TX) and receiver (RX) share a single antenna to reduce implant size. The TX uses impulse radio ultra-wide band (IR-UWB) based on an edge combining approach, and the RX uses a novel 2.4-GHz on-off keying (OOK) receiver. Proper isolation (&gt; 20 dB) between the TX and RX path is implemented 1) by shaping the transmitted pulses to fall within the unregulated UWB spectrum (3.1-7 GHz), and 2) by space-efficient filtering (avoiding a circulator or diplexer) of the downlink OOK spectrum in the RX low-noise amplifier (LNA). The UWB 3.1-7 GHz transmitter using OOK and binary phase shift keying (BPSK) modulations at only 10.8 pJ/bit. The proposed FDT provides dual band 500 Mbps TX uplink data rate and 100 Mbps RX downlink data rate. It is fully integrated on standard TSMC 0.18 nm CMOS within a total size of 0.8 mm2. The total power consumption measured 10.4 mW (5 mW for RX and 5.4 mW for TX at the rate of 500 Mbps)