Above-IC RF MEMS devices for communication applications

Wireless communications are showing an explosive growth in emerging consumer and military applications of radiofrequency (RF), microwave, and millimeter-wave circuits and systems. Applications include wireless personal connectivity (Bluetooth), wireless local area networks (WLAN), mobile communication systems (GSM, GPRS, UMTS, CDMA), satellite communications and automotive electronics. Future cell phones and ground communication systems as well as communication satellites will require more and more sophisticated technologies. The increasing demand for size and weight reduction, cost savings, low power consumption, increased frequency and higher functionality and reconfigurability as part of multiband and multistandard operation is necessitating the use of highly integrated RF front-end circuits. Chip scaling has made a major contribution to this goal, but today a situation has been reached where the presence of numerous off-chip passive RF components imposes a critical bottleneck to further integration and miniaturization of wireless transceivers. Microelectromechanical systems (MEMS) technology is a rapidly emerging enabling technology that is intended to replace the discrete passives by their integrated counterparts. In this thesis, an original metal surface micromachining process, which is compatible with CMOS post-processing, for above-IC integration of RF MEMS tunable capacitors and suspended inductors is presented. A detailed study on SF6 inductively coupled plasma (ICP) releasing has been performed in order to ascertain the optimal process parameters. This study has emphasized the fact that temperature plays an important role in this process by limiting silicon dioxide etching. Moreover, the optimized recipe has been found to be independent of the sacrificial layer used (amorphous or polycrystalline silicon) and its thickness. Using this recipe, 15.6 µm/min Si underetch rate with high Si: SiO2 selectivity (> 20000: 1) has been obtained. Single-air-gap and double-air-gap parallel-plate MEMS tunable capacitors have been designed, fabricated and characterized in the pF range, from 1 MHz to 13.5 GHz. It has been shown that an optimized design of the suspended membrane and direct symmetrical current feed at both ports can significantly improve the quality factor and increase the self-resonant frequency, pushing it to 12 GHz and beyond. The maximum capacitance tuning range obtained for a single-air-gap capacitor is 29% for a bias voltage of 20 V. The maximum capacitance tuning range obtained for a double-air-gap capacitor is 207% for a bias voltage of 70 V. The post-processing of X-FAB BiCMOS wafers has been successfully demonstrated to fabricate monolithically integrated VCOs with above-IC MEMS LC tank. Comparing a suspended inductor and the X-FAB inductor with the same design, it has been shown that increasing the thickness of the spiral from 2.3 to 4 µm and having the spiral suspended 3 µm above the passivation layers lead to an improvement factor of 2 for the peak quality factor and a shift of the self-resonant frequency beyond 15 GHz. No significant variation on bipolar and MOS transistors characteristics due to the post-processing has been observed and we conclude that the variation due to post-processing is in the same range as the wafer-to-wafer variation. Based on our metal surface micromachining process, coplanar waveguide (CPW) MEMS shunt capacitive switches and variable true-time delay lines (V-TTDLs) have been designed, fabricated and characterized in the 1 - 20 GHz range. A novel MEMS device architecture: the SG-MOSFET, which combines a solid-state MOS transistor and a metal suspended gate has been proposed as DC current switch. The corresponding fabrication process using polysilicon as a sacrificial layer has been developed to release metal gate suspended over gate oxide by SF6 plasma. Very abrupt current switches have been demonstrated with subthreshold slope better than 10 mV/decade (better than the theoretical solid-state bulk or SOI MOSFET limit of 60 mV/decade) and ultra-low gate leakage (less than 0.001 pA/µm2) due to the air-gap

Microwave CMOS VCOs and Front-Ends - using integrated passives on-chip and on-carrier

The increasing demand for high data rates in wireless communication systems is increasing the requirements on the transceiver front-ends, as they are pushed to utilize more and wider bands at higher frequencies. The work in this thesis is focused on receiver front-ends composed of Low Noise Amplifiers (LNAs), Mixers, and Voltage Controlled Oscillators (VCOs) operating at microwave frequencies. Traditionally, microwave electronics has used exclusive and more expensive semiconductor technologies (III-V materials). However, the rapid development of consumer electronics (e.g. video game consoles) the last decade has pushed the silicon CMOS IC technology towards even smaller feature sizes. This has resulted in high speed transistors (high fT and fmax) with low noise figures. However, as the breakdown voltages have decreased, a lower supply voltage must be used, which has had a negative impact on linearity and dynamic range. Nonetheless, todays downscaled CMOS technology is a feasible alternative for many microwave and even millimeter wave applications. The low quality factor (Q) of passive components on-chip usually limits the high frequency performance. For inductors realized in a standard CMOS process the substrate coupling results in a degraded Q. The quality factor can, however, be improved by moving the passive components off-chip and integrating them on a low loss carrier. This thesis therefore features microwave front-end and VCO designs in CMOS, where some designs have been flip-chip mounted on carriers featuring high Q inductors and low loss baluns. The thesis starts with an introduction to wireless communication, receiver architectures, front-end receiver blocks, and low loss carrier technology, followed by the included papers. The six included papers show the capability of CMOS and carrier technology at microwave frequencies: Papers II, III, and VI demonstrate fully integrated CMOS circuit designs. An LC-VCO using an accumulation mode varactor is presented in Paper II, a QVCO using 4-bit switched tuning is shown in Paper III, and a quadrature receiver front-end (including QVCO) is demonstrated in paper VI. Papers I and IV demonstrate receiver front-ends using low loss baluns on carrier for the LO and RF signals. Paper IV also includes a front-end using single-ended RF input which is converted to differential form in a novel merged LNA and balun. A VCO demonstrating the benefits of a high Q inductor on carrier is presented in Paper V

Voltage controlled oscillator for mm-wave radio systems

Abstract. The advancement in silicon technology has accelerated the development of integrated millimeter-wave transceiver systems operating up to 100 GHz with sophisticated functionality at a reduced consumer cost. Due to the progress in the field of signal processing, frequency modulated continuous wave (FMCW) radar has become common in recent years. A high-performance local oscillator (LO) is required to generate reference signals utilized in these millimeter-wave radar transceivers. To accomplish this, novel design techniques in fundamental voltage controlled oscillators (VCO) are necessary to achieve low phase noise, wide frequency tuning range, and good power efficiency. Although integrated VCOs have been studied for decades, as we move higher in the radio frequency spectrum, there are new trade-offs in the performance parameters that require further characterization. The work described in this thesis aims to design a fully integrated fundamental VCO targeting to 150 GHz, i.e., D-Band. The purpose is to observe and analyze the design limitations at these high frequencies and their corresponding trade-offs during the design procedure. The topology selected for this study is the cross-coupled LC tank VCO. For the study, two design topologies were considered: a conventional cross-coupled LC tank VCO and an inductive divider cross-coupled LC tank VCO. The conventional LC tank VCO yields better performance in terms of phase noise and tuning range. It is observed that the VCO is highly sensitive to parasitic contributions by the transistors, and the layout interconnects, thus limiting the targeted frequency range. The dimensions of the LC tank and the transistors are selected carefully. Moreover, the VCO performance is limited by the low Q factor of the LC tank governed by the varactor that is degrading the phase noise performance and the tuning range, respectively. The output buffer loaded capacitance and the core power consumption of the VCO are optimized. The layout is drawn carefully with strategies to minimize the parasitic effects. Considering all the design challenges, a 126 GHz VCO with a tuning range of 3.9% is designed. It achieves FOMT (Figure-of-merit) of -172 dBc/Hz, and phase noise of -99.14 dBc/Hz at 10 MHz offset, Core power consumption is 8.9 mW from a 1.2 V supply. Just falling short of the targeted frequency, the design is suitable for FMCW radar applications for future technologies. The design was done using Silicon-on-Insulator (SOI) CMOS technology

Study of radiation-tolerant integrated circuits for space applications

Integrated Circuits in space suffer from reliability problems due to the radiative surroundings. High energy particles can ionize the semiconductor and lead to single event effects. For digital systems, the transients can upset the logic values in the storage cells which are called single event upsets, or in the combinational logic circuits which are called single event transients. While for analog systems, the transient will introduce noises and change the operating point. The influence becomes more notable in advanced technologies, where devices are more susceptive to the perturbations due to the compact layout. Recently radiation-hardened-by-design has become an effective approach compared to that of modifying semiconductor processes. Hence it is used in this thesis project. Firstly, three elaborately designed radiation-tolerant registers are implemented. Then, two built-in testing circuits are introduced. They are used to detect and count the single event upsets in the registers during high-energy particle tests. The third part is the pulse width measurement circuit, which is designed for measuring the single event transient pulse width in combinational logic circuits. According to the simulations, transient pulse width ranging from 90.6ps to 2.53ns can be effectively measured. Finally, two frequently used cross-coupled LC tank voltage-controlled oscillators are studied to compare their radiation tolerances. Simulation results show that the direct power connection and transistors working in the deep saturation mode have positive influence toward the radiation tolerance. All of the circuit designs, simulations and analyses are based on STMicroelectronics CMOS 90 nm 7M2T General Process

High Performance Optical Transmitter Ffr Next Generation Supercomputing and Data Communication

High speed optical interconnects consuming low power at affordable prices are always a major area of research focus. For the backbone network infrastructure, the need for more bandwidth driven by streaming video and other data intensive applications such as cloud computing has been steadily pushing the link speed to the 40Gb/s and 100Gb/s domain. However, high power consumption, low link density and high cost seriously prevent traditional optical transceiver from being the next generation of optical link technology. For short reach communications, such as interconnects in supercomputers, the issues related to the existing electrical links become a major bottleneck for the next generation of High Performance Computing (HPC). Both applications are seeking for an innovative solution of optical links to tackle those current issues. In order to target the next generation of supercomputers and data communication, we propose to develop a high performance optical transmitter by utilizing CISCO Systems®\u27s proprietary CMOS photonic technology. The research seeks to achieve the following outcomes: 1. Reduction of power consumption due to optical interconnects to less than 5pJ/bit without the need for Ring Resonators or DWDM and less than 300fJ/bit for short distance data bus applications. 2. Enable the increase in performance (computing speed) from Peta-Flop to Exa-Flops without the proportional increase in cost or power consumption that would be prohibitive to next generation system architectures by means of increasing the maximum data transmission rate over a single fiber. 3. Explore advanced modulation schemes such as PAM-16 (Pulse-Amplitude-Modulation with 16 levels) to increase the spectrum efficiency while keeping the same or less power figure. This research will focus on the improvement of both the electrical IC and optical IC for the optical transmitter. An accurate circuit model of the optical device is created to speed up the performance optimization and enable co-simulation of electrical driver. Circuit architectures are chosen to minimize the power consumption without sacrificing the speed and noise immunity. As a result, a silicon photonic based optical transmitter employing 1V supply, featuring 20Gb/s data rate is fabricated. The system consists of an electrical driver in 40nm CMOS and an optical MZI modulator with an RF length of less than 0.5mm in 0.13&mu m SOI CMOS. Two modulation schemes are successfully demonstrated: On-Off Keying (OOK) and Pulse-Amplitude-Modulation-N (PAM-N N=4, 16). Both versions demonstrate signal integrity, interface density, and scalability that fit into the next generation data communication and exa-scale computing. Modulation power at 20Gb/s data rate for OOK and PAM-16 of 4pJ/bit and 0.25pJ/bit are achieved for the first time of an MZI type optical modulator, respectively

RF-MEMS Switch Module in a 0.25 µm SiGe:C BiCMOS Process

Drahtlose Kommunikationstechnologien im Frequenzbereich bis 6 GHz wurden in der Vergangenheit in Bezug auf Leistungsfaehigkeit und Frequenzbereich kontinuierlich verbessert. Aufgrund der Skalierung nach dem Mooreschen Gesetz koennen heutzutage mm-Wellen Schaltkreise in CMOS-Technologien hergestellt werden. Durch die Einfuehrung von SiGe zur Realisierung einer leistungsfaehigen BiCMOS-Technologie wurde ebenfalls eine Verbesserung der Frequenzeigenschaften und Ausgangsleistungen erreicht, wodurch aktive CMOS- oder BiCMOS-Bauelemente vergleichbare Leistungsparameter zu III-V Technologien bei geringeren Kosten bereitstellen koennen. Bedingt durch das niederohmige Silizium-Substrat der BiCMOS-Technologie weisen vor allem passive Komponenten hoehere Verluste auf und weder III-V- noch BiCMOS-Technologien bieten hochlineare Schaltkomponenten mit geringen Verlusten und geringen Leistungsaufnahmen im mm-Wellen Bereich. RF-MEMS Schalter sind bekannt fuer ihre ausgezeichneten HF-Eigenschaften. Die Leistungsaufnahme von elektrostatisch angetriebenen RF-MEMS Schaltern ist vernachlaessigbar und es koennen im Vergleich zu halbleiter-basierten Schaltern hoehere Leistungen verarbeitet werden. Nichtsdestotrotz wurden RF-MEMS Schalter hauptsaechlich als eigenstaendige Komponenten entwickelt. Zur Systemintegration wird meist ein System-in-Package (SiP) Ansatz angewandt, der fuer niedrige Frequenzen geeignet ist, aber bei mm-Wellenanwendungen durch parasitaere Verluste an seine Grenzen stoesst. In dieser Arbeit wird ein in eine BiCMOS-Technologie integrierter RF-MEMS Schalter fuer mm-Wellen Anwendungen gezeigt. Das Design, die Integration und die experimentellen Ergebnisse sowie verschiedene Packaging-Konzepte werden beschrieben Zur Bereitstellung der hohen Auslenkungs-Spannungen wurde eine Ladungspumpe auf dem Chip integriert. Zum Schluss werden verschiedene, rekonfigurierbare mm-Wellen Schaltkreise zur Demonstration der Leistungsfaehigkeit des Schalters gezeigt.Wireless communication technologies have continuously advanced for both performance and frequency aspects, mainly for the frequencies up to 6 GHz. The results of Moore’s law now also give the opportunity to design mm-wave circuits using advanced CMOS technologies. The introduction of SiGe into CMOS, providing high performance BiCMOS, has also enhanced both the frequency and the power performance figures. The current situation is that the active devices of both CMOS and BiCMOS technologies can provide performance figures competitive with III-V technologies while having still the advantage of low cost. However, similar competition cannot be pronounced for the passive components considering the low-resistive substrates of BiCMOS technologies. Moreover, both III-V and BiCMOS technologies have the lack of low-loss and low-power consumption, as well as highly linear switching and tuning components at mm-wave frequencies. RF-MEMS switch technologies have been well-known with excellent RF- performance figures. The power consumption of electrostatic RF-MEMS switches is negligible and they can handle higher power levels compared to their semiconductor counterparts. However, RF-MEMS switches have been mostly demonstrated as standalone processes and have started to be used as commercial off-the-shelf (COTS) devices recently. The full system integration is typically done by a System-in-Package (SiP) approach. Although SiP is suitable for lower frequencies, the packaging parasitics limit the use of this approach for the mm-wave frequencies. In this thesis, a fully BiCMOS embedded RF-MEMS switch for mm-wave applications is proposed. The design, the implementation and the experimental results of the switch are provided. The developed RF-MEMS switch is packaged using different packaging approaches. To actuate the RF-MEMS switch, an on-chip high voltage generation circuit is designed and characterized. The robustness and the reliability performance of the switch are also presented. Finally, the developed RF-MEMS switch is successfully demonstrated in re-configurable mm-wave circuits

Characterization of process variability and robust optimization of analog circuits

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (p. 161-174).Continuous scaling of CMOS technology has enabled dramatic performance enhancement of CMOS devices and has provided speed, power, and density improvement in both digital and analog circuits. CMOS millimeter-wave applications operating at more than 50GHz frequencies has become viable in sub-100nm CMOS technologies, providing advantages in cost and high density integration compared to other heterogeneous technologies such as SiGe and III-V compound semiconductors. However, as the operating frequency of CMOS circuits increases, it becomes more difficult to obtain sufficiently wide operating ranges for robust operation in essential analog building blocks such as voltage-controlled oscillators (VCOs) and frequency dividers. The fluctuations of circuit parameters caused by the random and systematic variations in key manufacturing steps become more significant in nano-scale technologies. The process variation of circuit performance is quickly becoming one of the main concerns in high performance analog design. In this thesis, we show design and analysis of a VCO and frequency divider operating beyond 70GHz in a 65nm SOI CMOS technology. The VCO and frequency divider employ design techniques enlarging frequency operating ranges to improve the robustness of circuit operation. Circuit performance is measured from a number of die samples to identify the statistical properties of performance variation. A back-propagation of variation (BPV) scheme based on sensitivity analysis of circuit performance is proposed to extract critical circuit parameter variation using statistical measurement results of the frequency divider. We analyze functional failure caused by performance variability, and propose dynamic and static optimization methods to improve parametric yield. An external bias control is utilized to dynamically tune the divider operating range and to compensate for performance variation. A novel time delay model of a differential CML buffer is proposed to functionally approximate the maximum operating frequency of the frequency divider, which dramatically reduces computational cost of parametric yield estimation. The functional approximation enables the optimization of the VCO and frequency divider parametric yield with a reasonable amount of simulation time.by Daihyun Lim.Ph.D

Integrated RF oscillators and LO signal generation circuits

This thesis deals with fully integrated LC oscillators and local oscillator (LO) signal generation circuits. In communication systems a good-quality LO signal for up- and down-conversion in transmitters is needed. The LO signal needs to span the required frequency range and have good frequency stability and low phase noise. Furthermore, most modern systems require accurate quadrature (IQ) LO signals. This thesis tackles these challenges by presenting a detailed study of LC oscillators, monolithic elements for good-quality LC resonators, and circuits for IQ-signal generation and for frequency conversion, as well as many experimental circuits. Monolithic coils and variable capacitors are essential, and this thesis deals with good structures of these devices and their proper modeling. As experimental test devices, over forty monolithic inductors and thirty varactors have been implemented, measured and modeled. Actively synthesized reactive elements were studied as replacements for these passive devices. At first glance these circuits show promising characteristics, but closer noise and nonlinearity analysis reveals that these circuits suffer from high noise levels and a small dynamic range. Nine circuit implementations with various actively synthesized variable capacitors were done. Quadrature signal generation can be performed with three different methods, and these are analyzed in the thesis. Frequency conversion circuits are used for alleviating coupling problems or to expand the number of frequency bands covered. The thesis includes an analysis of single-sideband mixing, frequency dividers, and frequency multipliers, which are used to perform the four basic arithmetical operations for the frequency tone. Two design cases are presented. The first one is a single-sideband mixing method for the generation of WiMedia UWB LO-signals, and the second one is a frequency conversion unit for a digital period synthesizer. The last part of the thesis presents five research projects. In the first one a temperature-compensated GaAs MESFET VCO was developed. The second one deals with circuit and device development for an experimental-level BiCMOS process. A cable-modem RF tuner IC using a SiGe process was developed in the third project, and a CMOS flip-chip VCO module in the fourth one. Finally, two frequency synthesizers for UWB radios are presented