Statistical modeling of static leakage power and its variability in CMOS circuits

This paper focuses on the impact of process variations on the estimation of static leakage power and its variability. A statistical methodology for the estimation of static leakage power dissipation due to subthreshold leakage and gate tunneling leakage in 65 nm CMOS digital circuits, in the presence of process variations, is presented. A 2-input NAND gate is used as a representative library element, whose leakage power is extensively characterized, by rigorous mixed-mode simulations. Also, an analytical model for leakage power is proposed at the gate level in terms of the device resistance data, for computational simplicity. The proposed methodology is demonstrated by characterizing the variations in the leakage power of a 4-bit � 4-bit Wallace tree multiplier by an extensive Monte Carlo analysis. To extend this methodology to a generic technology library for process characterization, an optimal second order hybrid model is proposed by combining a piece-wise quadratic model obtained by Least Squares Method (LSM) and Response Surface Modeling (RSM) of leakage power of NAND gate directly in terms of process parameters, using Design of Experiment (DOE). We demonstrate that our hybrid models based statistical design approach can result in upto 95 improvement in accurate prediction of variability with an error of less than 0.7, with respect to worst case design. In terms of standard deviation, the predictability of leakage power distributions get tighter by atleast 13X, leading to considerable savings in the power budget of low power CMOS designs. This work aims to bridge the manufacturing to design gap, through the characterization of standard cell libraries for leakage power, in the presence of process variations

Modeling of thermally induced skew variations in clock distribution network

Clock distribution network is sensitive to large thermal gradients on the die as the performance of both clock buffers and interconnects are affected by temperature. A robust clock network design relies on the accurate analysis of clock skew subject to temperature variations. In this work, we address the problem of thermally induced clock skew modeling in nanometer CMOS technologies. The complex thermal behavior of both buffers and interconnects are taken into account. In addition, our characterization of the temperature effect on buffers and interconnects provides valuable insight to designers about the potential impact of thermal variations on clock networks. The use of industrial standard data format in the interface allows our tool to be easily integrated into existing design flow

Synthetic biology and microdevices : a powerful combination

Recent developments demonstrate that the combination of microbiology with micro-and nanoelectronics is a successful approach to develop new miniaturized sensing devices and other technologies. In the last decade, there has been a shift from the optimization of the abiotic components, for example, the chip, to the improvement of the processing capabilities of cells through genetic engineering. The synthetic biology approach will not only give rise to systems with new functionalities, but will also improve the robustness and speed of their response towards applied signals. To this end, the development of new genetic circuits has to be guided by computational design methods that enable to tune and optimize the circuit response. As the successful design of genetic circuits is highly dependent on the quality and reliability of its composing elements, intense characterization of standard biological parts will be crucial for an efficient rational design process in the development of new genetic circuits. Microengineered devices can thereby offer a new analytical approach for the study of complex biological parts and systems. By summarizing the recent techniques in creating new synthetic circuits and in integrating biology with microdevices, this review aims at emphasizing the power of combining synthetic biology with microfluidics and microelectronics

Expansion of CMOS array design techniques

The important features of the multiport (double entry) automatic placement and routing programs for standard cells are described. Measured performance and predicted performance were compared for seven CMOS/SOS array types and hybrids designed with the high speed CMOS/SOS cell family. The CMOS/SOS standard cell data sheets are listed and described

Cross-Layer Resiliency Modeling and Optimization: A Device to Circuit Approach

The never ending demand for higher performance and lower power consumption pushes the VLSI industry to further scale the technology down. However, further downscaling of technology at nano-scale leads to major challenges. Reduced reliability is one of them, arising from multiple sources e.g. runtime variations, process variation, and transient errors. The objective of this thesis is to tackle unreliability with a cross layer approach from device up to circuit level

Statistical library characterization using belief propagation across multiple technology nodes

In this paper, we propose a novel flow to enable computationally efficient statistical characterization of delay and slew in standard cell libraries. The distinguishing feature of the proposed method is the usage of a limited combination of output capacitance, input slew rate and supply voltage for the extraction of statistical timing metrics of an individual logic gate. The efficiency of the proposed flow stems from the introduction of a novel, ultra-compact, nonlinear, analytical timing model, having only four universal regression parameters. This novel model facilitates the use of maximum-a-posteriori belief propagation to learn the prior parameter distribution for the parameters of the target technology from past characterizations of library cells belonging to various other technologies, including older ones. The framework then utilises Bayesian inference to extract the new timing model parameters using an ultra-small set of additional timing measurements from the target technology. The proposed method is validated and benchmarked on several production-level cell libraries including a state-of-the-art 14-nm technology node and a variation-aware, compact transistor model. For the same accuracy as the conventional lookup-table approach, this new method achieves at least 15x reduction in simulation runs.Masdar Institute of Science and Technology (Massachusetts Institute of Technology Cooperative Agreement

Statistical leakage estimation in 32nm CMOS considering cells correlations

International audienceIn this paper a method to estimate the leakage power consumption of CMOS digital circuits taking into account input states and process variations is proposed. The statistical leakage estimation is based on a pre-characterization of library cells considering correlations (ρ) between cells leakages. A method to create cells leakage correlation matrix is introduced. The maximum relative error achieved in the correlation matrix is 0.4% with respect to the correlations obtained by Monte Carlo simulations. Next the total circuit leakage is calculated from this matrix and cells leakage means and variances. The accuracy and efficiency of the approach is demonstrated on a C3540 (8 bit ALU) ISCAS85 Benchmark circuit