Low power VCO-based analog-to-digital conversion

textThis dissertation presents novel two stage ADC architecture with a VCO based second stage. With the scaling of the supply voltages in modern CMOS process it is difficult to design high gain operational amplifiers needed for traditional voltage domain two-stage analog to digital converters. However time resolution continues to improve with the advancement in CMOS technology making VCO-based ADC more attractive. The nonlinearity in voltage-to-frequency transfer function is the biggest challenge in design of VCO based ADC. The hybrid approach used in this work uses a voltage domain first stage to determine the most significant bits and uses a VCO based second stage to quantize the small residue obtained from first stage. The architecture relaxes the gain requirement on the the first stage opamp and also relaxes the linearity requirements on the second stage VCO. The prototype ADC built in 65nm CMOS process achieves 63.7dB SNDR in 10MHz bandwidth while only consuming 1.1mW of power. The performance of the prototype chip is comparable to the state-of-art in terms of figure-of-merit but this new architecture uses significantly less circuit area.Electrical and Computer Engineerin

Low-Power Slew-Rate Boosting Based 12-Bit Pipeline ADC Utilizing Forecasting Technique in the Sub-ADCS

The dissertation presents architecture and circuit solutions to improve the power efficiency of high-speed 12-bit pipelined ADCs in advanced CMOS technologies. First, the 4.5bit algorithmic pipelined front-end stage is proposed. It is shown that the algorithmic pipelined ADC requires a simpler sub-ADC and shows lower sensitivity to the Multiplying DAC (MDAC) errors and smaller area and power dissipation in comparison to the conventional multi-bit per stage pipelined ADC. Also, it is shown that the algorithmic pipelined architecture is more tolerant to capacitive mismatch for the same input-referred thermal noise than the conventional multi-bit per stage architecture. To take full advantage of these properties, a modified residue curve for the pipelined ADC is proposed. This concept introduces better linearity compared with the conventional residue curve of the pipelined ADC; this approach is particularly attractive for the digitization of signals with large peak to average ratio such as OFDM coded signals. Moreover, the minimum total required transconductance for the different architectures of the 12-bit pipelined ADC are computed. This helps the pipelined ADC designers to find the most power-efficient architecture between different topologies based on the same input-referred thermal noise. By employing this calculation, the most power efficient architecture for realizing the 12-bit pipelined ADC is selected. Then, a technique for slew-rate (SR) boosting in switched-capacitor circuits is proposed in the order to be utilized in the proposed 12-bit pipelined ADC. This technique makes use of a class-B auxiliary amplifier that generates a compensating current only when high slew-rate is demanded by large input signal. The proposed architecture employs simple circuitry to detect the need of injecting current at the output load by implementing a Pre-Amp followed by a class-B amplifier, embedded with a pre-defined hysteresis, in parallel with the main amplifier to boost its slew phase. The proposed solution requires small static power since it does not need high dc-current at the output stage of the main amplifier. The proposed technique is suitable for high-speed low-power multi-bit/stage pipelined ADC applications. Both transistor-level simulations and experimental results in TSMC 40nm technology reduces the slew-time for more than 45% and shorts the 1% settling time by 28% when used in a 4.5bit/stage pipelined ADC; power consumption increases by 20%. In addition, the technique of inactivating and disconnecting of the sub-ADC’s comparators by forecasting the sign of the sampled input voltage is proposed in the order to reduce the dynamic power consumption of the sub-ADCs in the proposed 12-bit pipelined ADC. This technique reduces the total dynamic power consumption more than 46%. The implemented 12-bit pipelined ADC achieves an SNDR/SFDR of 65.9/82.3 dB at low input frequencies and a 64.1/75.5 dB near Nyquist frequency while running at 500 MS/s. The pipelined ADC prototype occupies an active area of 0.9 mm^2 and consumes 18.16 mW from a 1.1 V supply, resulting in a figure of merit (FOM) of 22.4 and a 27.7 fJ/conversion-step at low-frequency and Nyquist frequency, respectively

Low-Power Slew-Rate Boosting Based 12-Bit Pipeline ADC Utilizing Forecasting Technique in the Sub-ADCS

The dissertation presents architecture and circuit solutions to improve the power efficiency of high-speed 12-bit pipelined ADCs in advanced CMOS technologies. First, the 4.5bit algorithmic pipelined front-end stage is proposed. It is shown that the algorithmic pipelined ADC requires a simpler sub-ADC and shows lower sensitivity to the Multiplying DAC (MDAC) errors and smaller area and power dissipation in comparison to the conventional multi-bit per stage pipelined ADC. Also, it is shown that the algorithmic pipelined architecture is more tolerant to capacitive mismatch for the same input-referred thermal noise than the conventional multi-bit per stage architecture. To take full advantage of these properties, a modified residue curve for the pipelined ADC is proposed. This concept introduces better linearity compared with the conventional residue curve of the pipelined ADC; this approach is particularly attractive for the digitization of signals with large peak to average ratio such as OFDM coded signals. Moreover, the minimum total required transconductance for the different architectures of the 12-bit pipelined ADC are computed. This helps the pipelined ADC designers to find the most power-efficient architecture between different topologies based on the same input-referred thermal noise. By employing this calculation, the most power efficient architecture for realizing the 12-bit pipelined ADC is selected. Then, a technique for slew-rate (SR) boosting in switched-capacitor circuits is proposed in the order to be utilized in the proposed 12-bit pipelined ADC. This technique makes use of a class-B auxiliary amplifier that generates a compensating current only when high slew-rate is demanded by large input signal. The proposed architecture employs simple circuitry to detect the need of injecting current at the output load by implementing a Pre-Amp followed by a class-B amplifier, embedded with a pre-defined hysteresis, in parallel with the main amplifier to boost its slew phase. The proposed solution requires small static power since it does not need high dc-current at the output stage of the main amplifier. The proposed technique is suitable for high-speed low-power multi-bit/stage pipelined ADC applications. Both transistor-level simulations and experimental results in TSMC 40nm technology reduces the slew-time for more than 45% and shorts the 1% settling time by 28% when used in a 4.5bit/stage pipelined ADC; power consumption increases by 20%. In addition, the technique of inactivating and disconnecting of the sub-ADC’s comparators by forecasting the sign of the sampled input voltage is proposed in the order to reduce the dynamic power consumption of the sub-ADCs in the proposed 12-bit pipelined ADC. This technique reduces the total dynamic power consumption more than 46%. The implemented 12-bit pipelined ADC achieves an SNDR/SFDR of 65.9/82.3 dB at low input frequencies and a 64.1/75.5 dB near Nyquist frequency while running at 500 MS/s. The pipelined ADC prototype occupies an active area of 0.9 mm^2 and consumes 18.16 mW from a 1.1 V supply, resulting in a figure of merit (FOM) of 22.4 and a 27.7 fJ/conversion-step at low-frequency and Nyquist frequency, respectively

Low power design techniques for analog-to-digital converters in submicron CMOS

Advances in process technologies have led to the development of low-power high speed digital signal processing blocks that occupy small areas. These advances are critical in the development of portable electronic devices with small feature size and long battery life. However, the design of analog and mixed-signal building blocks, especially analog-to-digital converters (ADCs), becomes complex and power-inefficient with each advance in process node. This is because of decreased headroom and low intrinsic gain. In this thesis, circuit techniques that enable the design of low-complexity power-efficient ADCs in submicron CMOS are introduced. The techniques include improved correlated level shifting that allow the use of simple low gain amplifiers to realize high performance pipelined and delta-sigma ADCs. Also included is an investigation of the possibility of replacing the power-hungry amplifier in integrators, used in delta-sigma modulators, with low power zero-crossing-based ones. Simulation results of a correlated level shifting pipelined ADC and measurement results of a fabricated prototype of a zero-crossing-based delta-sigma ADC are employed to discuss the effectiveness of the techniques in achieving compact low-power designs

Amplifier Design for a Pipeline ADC in 90nm Technology

This paper explains the choices taken for the design of two full differential operational amplifiers. These op amp have been designed for the third and the fifth stage of a pipelined A/D Converter. It shows also the solutions found to reach high gain, wide bandwidth and short settling time, without degrading too much the output swing. First the operational amplifier specification are extracted starting from the ADC architecture, then the issues related to the sub-micrometrical design are analysed; the different structures tested are then presented and the motivation of the final topology choice are shown. It presents then the op amp schematic implementation, the simulation results and the layout with the 90nm TSMC design ki

Energy and area efficient techniques for data converters

Data converters are ubiquitous building blocks of a signal chain. The rapid increase in communication and connectivity devices presents new avenues for pushing the state of the art analog to digital converters. Techniques for improving resolution, bandwidth, linearity and bit-error rate, while reducing the power, energy and area is the motivation for this research. This research focuses on achieving this goal by enabling circuit techniques, architecture techniques and calibration methods. The following techniques are proposed for enabling power, area and energy efficient analog to digital converter techniques. 1. A capacitor switching scheme for successive approximation ADC is introduced to enable 93.4% energy reduction and 75 % reduction in capacitor area as compared to a conventional SAR ADCs. 2. Asynchronous correlated level shifting technique for improving current source linearity and power supply rejection ratio of zero crossing based circuits is proposed. This technique enables asynchronous ADC architectures for energy efficient system. 3. Unified gain enhancement model is proposed to catalogue gain enhancement techniques. Class-A+ and Replicated Parallel Gain Enhancement (RPGe) amplifiers are introduced as parallel gain enhancement techniques for switched capacitor circuits. A prototype pipelined ADC using RPGE amplifier achieves 74.9 dB SNDR, 90.8 dB SFDR, 87 dB THD at 20 MS/s. Built in 1P4M 0.18 μm technology and operating at 1.3 V supply, the ADC consumes 5.9 mW. The ADC occupies 3.06 sq. mm and has a figure of merit of 65 fJ /conversion step. Extracted simulation results of the prototype pipeline ADC using dynamic RPGE amplifier achieve 74 dB SNDR, 90 dB SFDR, and 85 dB THD at 30 MS /s in a 0.18 μm process. The ADC consumes 6.6 mW from a 1.3 V supply and achieves a figure of merit of 40 fJ/C-S. 4. A low-gain amplifier based V-T converter is utilized along with a TDC to replace the function of flash ADC and the DAC references in a pipeline ADC. The simulated/ extracted performance of the chip is 12bit, 100 MHz in 65nm process while consuming approximately 8-9 mA from 1 V supply. 5. A measurement technique for detecting and correcting bit-error rate in ADCs is proposed. This multi-path ADC technique squares the bit-error rate of the ADC without consuming additional analog power. The area increase is negligible compared to the conventional modular redundancy techniques. This technique can be applied to digitally detect and correct single event transients for ADCs. A three-path ADC can restore the ADC performance independent of the input frequency and number of errors in a single path. 6. LMS algorithm is used to estimate the VCO non-linearity by using the VCO as a Nyquist ADC and utilizing a slow but accurate ADC. The simulated ADC performance improves from 5 bits to 7.8 bits by using a second order fit to the VCO non-linearity

Design of a Cost-Efficient Reconfigurable Pipeline ADC

Power budget is very critical in the design of battery-powered implantable biomedical instruments. High speed, high resolution and low power usually cannot be achieved at the same time. Therefore, a tradeoff must be made to compromise every aspect of those features. As the main component of the bioinstrument, high conversion rate, high resolution ADC consumes most of the power. Fortunately, based on the operation modes of the bioinstrument, a reconfigurable ADC can be used to solve this problem. The reconfigurable ADC will operate at 10-bit 40 MSPS for the diagnosis mode and at 8-bit 2.5 MSPS for the monitor mode. The ADC will be completely turned off if no active signal comes from sensors or if an off command is received from the antenna. By turning off the sample hold stage and the first two stages of the pipeline ADC, a significant power saving is achieved. However, the reconfigurable ADC suffers from two drawbacks. First, the leakage signals through the extra off-state switches in the third stage degrade the performance of the data converter. This situation tends to be even worse for high speed and high-resolution applications. An interference elimination technique has been proposed in this work to solve this problem. Simulation results show a significant attenuation of the spurious tones. Moreover, the transistors in the OTA tend to operate in weak inversion region due to the scaling of the bias current. The transistor in subthreshold is very slow due to the small transit frequency. In order to get a better tradeoff between the transconductance efficiency and the transit frequency, reconfigurable OTAs and scalable bias technique are devised to adjust the operating point from weak inversion to moderate inversion. The figure of merit of the reconfigurable ADC is comparable to the previously published conventional pipeline ADCs. For the 10-bit, 40 MSPS mode, the ADC attains a 56.9 dB SNDR for 35.4 mW power consumption. For the 8-bit 2.5 MSPS mode, the ADC attains a 49.2 dB SNDR for 7.9 mW power consumption. The area for the core layout is 1.9 mm2 for a 0.35 micrometer process

A Low-Power, Reconfigurable, Pipelined ADC with Automatic Adaptation for Implantable Bioimpedance Applications

Biomedical monitoring systems that observe various physiological parameters or electrochemical reactions typically cannot expect signals with fixed amplitude or frequency as signal properties can vary greatly even among similar biosignals. Furthermore, advancements in biomedical research have resulted in more elaborate biosignal monitoring schemes which allow the continuous acquisition of important patient information. Conventional ADCs with a fixed resolution and sampling rate are not able to adapt to signals with a wide range of variation. As a result, reconfigurable analog-to-digital converters (ADC) have become increasingly more attractive for implantable biosensor systems. These converters are able to change their operable resolution, sampling rate, or both in order convert changing signals with increased power efficiency. Traditionally, biomedical sensing applications were limited to low frequencies. Therefore, much of the research on ADCs for biomedical applications focused on minimizing power consumption with smaller bias currents resulting in low sampling rates. However, recently bioimpedance monitoring has become more popular because of its healthcare possibilities. Bioimpedance monitoring involves injecting an AC current into a biosample and measuring the corresponding voltage drop. The frequency of the injected current greatly affects the amplitude and phase of the voltage drop as biological tissue is comprised of resistive and capacitive elements. For this reason, a full spectrum of measurements from 100 Hz to 10-100 MHz is required to gain a full understanding of the impedance. For this type of implantable biomedical application, the typical low power, low sampling rate analog-to-digital converter is insufficient. A different optimization of power and performance must be achieved. Since SAR ADC power consumption scales heavily with sampling rate, the converters that sample fast enough to be attractive for bioimpedance monitoring do not have a figure-of-merit that is comparable to the slower converters. Therefore, an auto-adapting, reconfigurable pipelined analog-to-digital converter is proposed. The converter can operate with either 8 or 10 bits of resolution and with a sampling rate of 0.1 or 20 MS/s. Additionally, the resolution and sampling rate are automatically determined by the converter itself based on the input signal. This way, power efficiency is increased for input signals of varying frequency and amplitude

Analysis and design of low-power data converters

In a large number of applications the signal processing is done exploiting both analog and digital signal processing techniques. In the past digital and analog circuits were made on separate chip in order to limit the interference and other side effects, but the actual trend is to realize the whole elaboration chain on a single System on Chip (SoC). This choice is driven by different reasons such as the reduction of power consumption, less silicon area occupation on the chip and also reliability and repeatability. Commonly a large area in a SoC is occupied by digital circuits, then, usually a CMOS short-channel technological processes optimized to realize digital circuits is chosen to maximize the performance of the Digital Signal Proccessor (DSP). Opposite, the short-channel technology nodes do not represent the best choice for analog circuits. But in a large number of applications, the signals which are treated have analog nature (microphone, speaker, antenna, accelerometers, biopotential, etc.), then the input and output interfaces of the processing chip are analog/mixed-signal conversion circuits. Therefore in a single integrated circuit (IC) both digital and analog circuits can be found. This gives advantages in term of total size, cost and power consumption of the SoC. The specific characteristics of CMOS short-channel processes such as: • Low breakdown voltage (BV) gives a power supply limit (about 1.2 V). • High threshold voltage VTH (compared with the available voltage supply) fixed in order to limit the leakage power consumption in digital applications (of the order of 0.35 / 0.4V), puts a limit on the voltage dynamic, and creates many problems with the stacked topologies. • Threshold voltage dependent on the channel length VTH = f(L) (short channel effects). • Low value of the output resistance of the MOS (r0) and gm limited by speed saturation, both causes contribute to achieving a low intrinsic gain gmr0 = 20 to 26dB. • Mismatch which brings offset effects on analog circuits. make the design of high performance analog circuits very difficult. Realizing lowpower circuits is fundamental in different contexts, and for different reasons: lowering the power dissipation gives the capability to reduce the batteries size in mobile devices (laptops, smartphones, cameras, measuring instruments, etc.), increase the life of remote sensing devices, satellites, space probes, also allows the reduction of the size and weight of the heat sink. The reduction of power dissipation allows the realization of implantable biomedical devices that do not damage biological tissue. For this reason, the analysis and design of low power and high precision analog circuits is important in order to obtain high performance in technological processes that are not optimized for such applications. Different ways can be taken to reduce the effect of the problems related to the technology: • Circuital level: a circuit-level intervention is possible to solve a specific problem of the circuit (i.e. Techniques for bandwidth expansion, increase the gain, power reduction, etc.). • Digital calibration: it is the highest level to intervene, and generally going to correct the non-ideal structure through a digital processing, these aims are based on models of specific errors of the structure. • Definition of new paradigms. This work has focused the attention on a very useful mixed-signal circuit: the pipeline ADC. The pipeline ADCs are widely used for their energy efficiency in high-precision applications where a resolution of about 10-16 bits and sampling rates above hundreds of Mega-samples per second (telecommunication, radar, etc.) are needed. An introduction on the theory of pipeline ADC, its state of the art and the principal non-idealities that affect the energy efficiency and the accuracy of this kind of data converters are reported in Chapter 1. Special consideration is put on low-voltage low-power ADCs. In particular, for ADCs implemented in deep submicron technology nodes side effects called short channel effects exist opposed to older technology nodes where undesired effects are not present. An overview of the short channel effects and their consequences on design, and also power consuption reduction techniques, with particular emphasis on the specific techniques adopted in pipelined ADC are reported in Chapter 2. Moreover, another way may be undertaken to increase the accuracy and the efficiency of an ADC, this way is the digital calibration. In Chapter 3 an overview on digital calibration techniques, and furthermore a new calibration technique based on Volterra kernels are reported. In some specific applications, such as software defined radios or micropower sensor, some circuits should be reconfigurable to be suitable for different radio standard or process signals with different charateristics. One of this building blocks is the ADC that should be able to reconfigure the resolution and conversion frequency. A reconfigurable voltage-scalable ADC pipeline capable to adapt its voltage supply starting from the required conversion frequency was developed, and the results are reported in Chapter 4. In Chapter 5, a pipeline ADC based on a novel paradigm for the feedback loop and its theory is described

?????? ?????? ???????????? ?????? ???????????? ??????????????? ?????????????????? ??? ???????????????

Department of Electrical EngineeringA Sensor system is advanced along sensor technologies are developed. The performance improvement of sensor system can be expected by using the internet of things (IoT) communication technology and artificial neural network (ANN) for data processing and computation. Sensors or systems exchanged the data through this wireless connectivity, and various systems and applications are possible to implement by utilizing the advanced technologies. And the collected data is computed using by the ANN and the efficiency of system can be also improved. Gas monitoring system is widely need from the daily life to hazardous workplace. Harmful gas can cause a respiratory disease and some gas include cancer-causing component. Even though it may cause dangerous situation due to explosion. There are various kinds of hazardous gas and its characteristics that effect on human body are different each gas. The optimal design of gas monitoring system is necessary due to each gas has different criteria such as the permissible concentration and exposure time. Therefore, in this thesis, conventional sensor system configuration, operation, and limitation are described and gas monitoring system with wireless connectivity and neural network is proposed to improve the overall efficiency. As I already mentioned above, dangerous concentration and permissible exposure time are different depending on gas types. During the gas monitoring, gas concentration is lower than a permissible level in most of case. Thus, the gas monitoring is enough with low resolution for saving the power consumption in this situation. When detecting the gas, the high-resolution is required for the accurate concentration detecting. If the gas type is varied in the above situation, the amount of calculation increases exponentially. Therefore, in the conventional systems, target specifications are decided by the highest requirement in the whole situation, and it occurs increasing the cost and complexity of readout integrated circuit (ROIC) and system. In order to optimize the specification, the ANN and adaptive ROIC are utilized to compute the complex situation and huge data processing. Thus, gas monitoring system with learning-based algorithm is proposed to improve its efficiency. In order to optimize the operation depending on situation, dual-mode ROIC that monitoring mode and precision mode is implemented. If the present gas concentration is decided to safe, monitoring mode is operated with minimal detecting accuracy for saving the power consumption. The precision mode is switched when the high-resolution or hazardous situation are detected. The additional calibration circuits are necessary for the high-resolution implementation, and it has more power consumption and design complexity. A high-resolution Analog-to-digital converter (ADC) is kind of challenges to design with efficiency way. Therefore, in order to reduce the effective resolution of ADC and power consumption, zooming correlated double sampling (CDS) circuit and prediction successive approximation register (SAR) ADC are proposed for performance optimization into precision mode. A Microelectromechanical systems (MEMS) based gas sensor has high-integration and high sensitivity, but the calibration is needed to improve its low selectivity. Conventionally, principle component analysis (PCA) is used to classify the gas types, but this method has lower accuracy in some case and hard to verify in real-time. Alternatively, ANN is powerful algorithm to accurate sensing through collecting the data and training procedure and it can be verified the gas type and concentration in real-time. ROIC was fabricated in complementary metal-oxide-semiconductor (CMOS) 180-nm process and then the efficiency of the system with adaptive ROIC and ANN algorithm was experimentally verified into gas monitoring system prototype. Also, Bluetooth supports wireless connectivity to PC and mobile and pattern recognition and prediction code for SAR ADC is performed in MATLAB. Real-time gas information is monitored by Android-based application in smartphone. The dual-mode operation, optimization of performance and prediction code are adjusted with microcontroller unit (MCU). Monitoring mode is improved by x2.6 of figure-of-merits (FoM) that compared with previous resistive interface.clos