Toward a new generation of photonic devices based on the integration of metal oxides in silicon technology

[ES] La búsqueda de nuevas soluciones e ideas innovadoras en el campo de la fotónica de silicio mediante la integración de nuevos materiales con prestaciones únicas es un tema de alta actualidad entre la comunidad científica en fotónica y con un impacto potencial muy alto. Dentro de esta temática, esta tesis pretende contribuir hacia una nueva generación de dispositivos fotónicos basados en la integración de óxidos metálicos en tecnología de silicio. Los óxidos metálicos elegidos pertenecen a la familia de óxidos conductores transparentes (TCO), concretamente el óxido de indio y estaño (ITO) y el óxido de cadmio (CdO), y materiales de cambio de fase (PCM) como el dióxido de vanadio (VO2). Dichos materiales se caracterizan especialmente por una variación drástica de sus propiedades optoelectrónicas, tales como la resistividad o el índice de refracción, frente a un estímulo externo ya sea en forma de temperatura, aplicación de un campo eléctrico o excitación óptica. De esta forma, nuestro objetivo es diseñar, fabricar y demostrar experimentalmente nuevas soluciones y dispositivos clave tales como dispositivos no volátiles, desfasadores y dispositivos con no linealidad óptica. Tales dispositivos podrían encontrar potencial utilidad en diversas aplicaciones que comprenden las comunicaciones ópticas, redes neuronales, LiDAR, computación, cuántica, entre otros. Las prestaciones clave en las que se pretende dar un salto disruptivo son el tamaño y capacidad para una alta densidad de integración, el consumo de potencia, y el ancho de banda.[CA] La recerca de noves solucions i idees innovadores al camp de la fotònica de silici mitjançant la integració de nous materials amb prestacions úniques és un tema d'alta actualitat entre la comunitat científica en fotònica i amb un impacte potencial molt alt. D'aquesta temàtica, aquesta tesi pretén contribuir cap a una nova generació de dispositius fotònics basats en la integració d'òxids metàl·lics en tecnologia de silici. Els òxids metàl·lics elegits pertanyen a la família d'òxids conductors transparents (TCO), concretament l'òxid d'indi i estany (ITO) i l'òxid de cadmi (CdO), i materials de canvi de fase (PCM) com el diòxid de vanadi (VO2). Aquests materials es caracteritzen especialment per una variació dràstica de les propietats optoelectròniques, com ara la resistivitat o l'índex de refracció, davant d'un estímul extern ja siga en forma de temperatura, aplicació d'un camp elèctric o excitació òptica. D'aquesta manera, el nostre objectiu és dissenyar, fabricar i demostrar experimentalment noves solucions i dispositius clau com ara dispositius no volàtils, desfasadors i dispositius amb no-linealitat òptica. Aquests dispositius podrien trobar potencial utilitat en diverses aplicacions que comprenen les comunicacions òptiques, xarxes neuronals, LiDAR, computació, quàntica, entre d'altres. Les prestacions clau en què es pretén fer un salt disruptiu són la grandària i la capacitat per a una alta densitat d'integració, el consum de potència i l'amplada de banda.[EN] The search for new solutions and innovative ideas in the field of silicon photonics through the integration of new materials featuring unique optoelectronic properties is a hot topic among the photonics scientific community with a very high potential impact. Within this topic, this thesis aims to contribute to a new generation of photonic devices based on the integration of metal oxides in silicon technology. The chosen metal oxides belong to the family of transparent conducting oxides (TCOs), namely indium tin oxide (ITO) and cadmium oxide (CdO), and phase change materials (PCMs) such as vanadium dioxide (VO2). These materials are characterized by a drastic variation of their optoelectronic properties, such as resistivity or refractive index, in response to an external stimulus either in the form of temperature, application of an electric field, or optical excitation. Therefore, our objective is to design, fabricate and experimentally demonstrate new solutions and key devices such as non-volatile devices, phase shifters, and devices with optical nonlinearity. Such devices could find potential utility in several applications, including optical communications, neural networks, LiDAR, computing, and quantum. The key features in which we aim to take a leapfrog are footprint and capacity for high integration density, power consumption, and bandwidth.This work is supported in part by grants ACIF/2018/172 funded by Generaliltat Valenciana, and FPU17/04224 funded by MCIN/AEI/10.13039/501100011033 and by “ESF Investing in your future”.Parra Gómez, J. (2022). Toward a new generation of photonic devices based on the integration of metal oxides in silicon technology [Tesis doctoral]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/19088

Design and Implementation of Low Power SRAM Using Highly Effective Lever Shifters

The explosive growth of battery-operated devices has made low-power design a priority in recent years. In high-performance Systems-on-Chip, leakage power consumption has become comparable to the dynamic component, and its relevance increases as technology scales. These trends are even more evident for SRAM memory devices since they are a dominant source of standby power consumption in low-power application processors. The on-die SRAM power consumption is particularly important for increasingly pervasive mobile and handheld applications where battery life is a key design and technology attribute. In the SRAM-memory design, SRAM cells also comprise the most significant portion of the total chip. Moreover, the increasing number of transistors in the SRAM memories and the MOSs\u27 increasing leakage current in the scaled technologies have turned the SRAM unit into a power-hungry block for both dynamic and static viewpoints. Although the scaling of the supply voltage enables low-power consumption, the SRAM cells\u27 data stability becomes a major concern. Thus, the reduction of SRAM leakage power has become a critical research concern. To address the leakage power consumption in high-performance cache memories, a stream of novel integrated circuit and architectural level techniques are proposed by researchers including leakage-current management techniques, cell array leakage reduction techniques, bitline leakage reduction techniques, and leakage current compensation techniques. The main goal of this work was to improve the cell array leakage reduction techniques in order to minimize the leakage power for SRAM memory design in low-power applications. This study performs the body biasing application to reduce leakage current as well. To adjust the NMOSs\u27 threshold voltage and consequently leakage current, a negative DC voltage could be applied to their body terminal as a second gate. As a result, in order to generate a negative DC voltage, this study proposes a negative voltage reference that includes a trimming circuit and a negative level shifter. These enhancements are employed to a 10kb SRAM memory operating at 0.3V in a 65nm CMOS process

Dynamic Partial Reconfiguration for Dependable Systems

Moore’s law has served as goal and motivation for consumer electronics manufacturers in the last decades. The results in terms of processing power increase in the consumer electronics devices have been mainly achieved due to cost reduction and technology shrinking. However, reducing physical geometries mainly affects the electronic devices’ dependability, making them more sensitive to soft-errors like Single Event Transient (SET) of Single Event Upset (SEU) and hard (permanent) faults, e.g. due to aging effects. Accordingly, safety critical systems often rely on the adoption of old technology nodes, even if they introduce longer design time w.r.t. consumer electronics. In fact, functional safety requirements are increasingly pushing industry in developing innovative methodologies to design high-dependable systems with the required diagnostic coverage. On the other hand commercial off-the-shelf (COTS) devices adoption began to be considered for safety-related systems due to real-time requirements, the need for the implementation of computationally hungry algorithms and lower design costs. In this field FPGA market share is constantly increased, thanks to their flexibility and low non-recurrent engineering costs, making them suitable for a set of safety critical applications with low production volumes. The works presented in this thesis tries to face new dependability issues in modern reconfigurable systems, exploiting their special features to take proper counteractions with low impacton performances, namely Dynamic Partial Reconfiguration

CMOS Data Converters for Closed-Loop mmWave Transmitters

With the increased amount of data consumed in mobile communication systems, new solutions for the infrastructure are needed. Massive multiple input multiple output (MIMO) is seen as a key enabler for providing this increased capacity. With the use of a large number of transmitters, the cost of each transmitter must be low. Closed-loop transmitters, featuring high-speed data converters is a promising option for achieving this reduced unit cost.In this thesis, both digital-to-analog (D/A) and analog-to-digital (A/D) converters suitable for wideband operation in millimeter wave (mmWave) massive MIMO transmitters are demonstrated. A 2 76 bit radio frequency digital-to-analog converter (RF-DAC)-based in-phase quadrature (IQ) modulator is demonstrated as a compact building block, that to a large extent realizes the transmit path in a closed-loop mmWave transmitter. The evaluation of an successive-approximation register (SAR) analog-to-digital converter (ADC) is also presented in this thesis. Methods for connecting simulated and measured performance has been studied in order to achieve a better understanding about the alternating comparator topology.These contributions show great potential for enabling closed-loop mmWave transmitters for massive MIMO transmitter realizations

Low Power Continuous-time Bandpass Delta-Sigma Modulators.

Low power techniques for continuous-time bandpass delta-sigma modulators (CTBPDSMs) are introduced. First, a 800MS/s low power 4th-order CTBPDSM with 24MHz bandwidth at 200MHz IF is presented. A novel power-efficient resonator with a single amplifier is used in the loopfilter. A single op-amp resonator makes use of positive feedback to increase the quality factor. Also, a new 4th-order architecture is introduced for system simplicity and low power. Low power consumption and a simple modulator structure are achieved by reducing the number of feedback DACs. This modulator achieves 58dB SNDR, and the total power consumption is 12mW. Second, a 6th-order CTBPDSM with duty cycle controlled DACs is presented. This prototype introduces new architecture for low power consumption and other important features. Duty cycle control enables the use of a single DAC per resonator without degrading the signal transfer function (STF), and helps to lower power consumption, low area, and thermal noise. This ADC provides input signal filtering, and increases the dynamic range by reducing the peaking in the STF. Furthermore, the center frequency is tunable so that the CTBPDSM is more useful in the receiver. The prototype second modulator achieves 69dB SNDR, and consumes 35mW, demonstrating the best FoM of 320fJ/conv.-step for CTBPDSMs using active resonators. The techniques introduced in this research help CTBPDSMs have good power efficiency compared with the other kinds of ADCs, and make the implement of a software-defined radio architecture easier which is appropriate for the future multiple standard radio receivers without a power penalty.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/98001/1/hichae_1.pd

Investigating ferroelectric and metal-insulator phase transition devices for neuromorphic computing

Neuromorphic computing has been proposed to accelerate the computation for deep neural networks (DNNs). The objective of this thesis work is to investigate the ferroelectric and metal-insulator phase transition devices for neuromorphic computing. This thesis proposed and experimentally demonstrated the drain erase scheme in FeFET to enable the individual cell program/erase/inhibition for in-situ training in 3D NAND-like FeFET array. To achieve multi-level states for analog in-memory computing, the ferroelectric thin film needs to be partially switched. This thesis identified a new challenge of ferroelectric partial switching, namely “history effect” in minor loop dynamics. The experimental characterization of both FeCap and FeFET validated the history effect, suggesting that the intermediate states programming condition depends on the prior states that the device has gone through. A phase-field model was constructed to understand the origin. Such history effect was then modelled into the FeFET based neural network simulation and analyze its negative impact on the training accuracy and then propose a possible mitigation strategy. Apart from using FeFET as synaptic devices, using metal-insulator phase transition device, as neuron was also explored experimentally. A NbOx metal-insulator phase transition threshold switch was integrated at the edge of the crossbar array as an oscillation neuron. One promising application for FeFET+NbOx neuromorphic system is to implement quantum error correction (QEC) circuitry at 4K. Cryo-NeuroSim, a device-to-system modeling framework that calibrates data at cryogenic temperature was developed to benchmark the performance of the FeFET+NbOx neuromorphic system.Ph.D

Autonomous smart antenna systems for future mobile devices

Along with the current trend of wireless technology innovation, wideband, compact size, low-profile, lightweight and multiple functional antenna and array designs are becoming more attractive in many applications. Conventional wireless systems utilise omni-directional or sectored antenna systems. The disadvantage of such antenna systems is that the electromagnetic energy, required by a particular user located in a certain direction, is radiated unnecessarily in every direction within the entire cell, hence causing interference to other users in the system. In order to limit this source of interference and direct the energy to the desired user, smart antenna systems have been investigated and developed. This thesis presents the design, simulation, fabrication and full implementation of a novel smart antenna system for future mobile applications. The design and characterisation of a novel antenna structure and four-element liner array geometry for smart antenna systems are proposed in the first stage of this study. Firstly, a miniaturised microstrip-fed planar monopole antenna with Archimedean spiral slots to cover WiFi/Bluetooth and LTE mobile applications has been demonstrated. The fundamental structure of the proposed antenna element is a circular patch, which operates in high frequency range, for the purpose of miniaturising the circuit dimension. In order to achieve a multi-band performance, Archimedean spiral slots, acting as resonance paths, have been etched on the circular patch antenna. Different shapes of Archimedean spiral slots have been investigated and compared. The miniaturised and optimised antenna achieves a bandwidth of 2.2GHz to 2.9GHz covering WiFi/Bluetooth (2.45GHz) and LTE (2.6GHz) mobile standards. Then a four-element linear antenna array geometry utilising the planar monopole elements with Archimedean spiral slots has been described. All the relevant parameters have been studied and evaluated. Different phase shifts are excited for the array elements, and the main beam scanning range has been simulated and analysed. The second stage of the study presents several feeding network structures, which control the amplitude and phase excitations of the smart antenna elements. Research begins with the basic Wilkinson power divider configuration. Then this thesis presents a compact feeding network for circular antenna array, reconfigurable feeding networks for tuning the operating frequency and polarisations, a feeding network on high resistivity silicon (HRS), and an ultrawide-band (UWB) feeding network covering from 0.5GHz to 10GHz. The UWB feeding network is used to establish the smart antenna array system. Different topologies of phase shifters are discussed in the third stage, including ferrite phase shifters and planar phase shifters using switched delay line and loaded transmission line technologies. Diodes, FETs, MMIC and MEMS are integrated into different configurations. Based on the comparison, a low loss and high accurate Hittite MMIC analogue phase shifter has been selected and fully evaluated for this implementation. For the purpose of impedance matching and field matching, compact and ultra wideband CPW-to-Microstrip transitions are utilised between the phase shifters, feeding network and antenna elements. Finally, the fully integrated smart antenna array achieves a 10dB reflection coefficient from 2.25GHz to 2.8GHz, which covers WiFi/Bluetooth (2.45GHz) and LTE (2.6GHz) mobile applications. By appropriately controlling the voltage on the phase shifters, the main beam of the antenna array is steered ±50° and ±52°, for 2.45GHz and 2.6GHz, respectively. Furthermore, the smart antenna array demonstrates a gain of 8.5dBi with 40° 3dB bandwidth in broadside direction, and has more than 10dB side lobe level suppression across the scan. The final stage of the study investigates hardware and software automatic control systems for the smart antenna array. Two microcontrollers PIC18F4550 and LPC1768 are utilised to build the control PCBs. Using the graphical user interfaces provided in this thesis, it is able to configure the beam steering of the smart antenna array, which allows the user to analyse and optimise the signal strength of the received WiFi signals around the mobile device. The design strategies proposed in this thesis contribute to the realisation of adaptable and autonomous smart phone systems