172 research outputs found
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CMOS Signal Synthesizers for Emerging RF-to-Optical Applications
The need for clean and powerful signal generation is ubiquitous, with applications spanning the spectrum from RF to mm-Wave, to into and beyond the terahertz-gap. RF applications including mobile telephony and microprocessors have effectively harnessed mixed-signal integration in CMOS to realize robust on-chip signal sources calibrated against adverse ambient conditions. Combined with low cost and high yield, the CMOS component of hand-held devices costs a few cents per part per million parts. This low cost, and integrated digital processing, make CMOS an attractive option for applications like high-resolution imaging and ranging, and the emerging 5-G communication space. RADAR techniques when expanded to optical frequencies can enable micrometers of resolution for 3D imaging. These applications, however, impose upto 100x more exacting specifications on power and spectral purity at much higher frequencies than conventional RF synthesizers.
This generation of applications will present unconventional challenges for transistor technologies - whether it is to squeeze performance in the conventionally used spectrum, already wrung dry, or signal generation and system design in the relatively emptier mm-Wave to sub-mmWave spectrum, much of the latter falling in the ``Terahertz Gap". Indeed, transistor scaling and innovative device physics leading to new transistor topologies have yielded higher cut-off frequencies in CMOS, though still lagging well behind SiGe and III-V semiconductors. To avoid multimodule solutions with functionality partitioned across different technologies, CMOS must be pushed out of its comfort zone, and technology scaling has to have accompanying breakthroughs in design approaches not only at the system but also at the block level. In this thesis, while not targeting a specific application, we seek to formulate the obstacles in synthesizing high frequency, high power and low noise signals in CMOS and construct a coherent design methodology to address them. Based on this, three novel prototypes to overcome the limiting factors in each case are presented.
The first half of this thesis deals with high frequency signal synthesis and power generation in CMOS. Outside the range of frequencies where the transistor has gain, frequency generation necessitates harmonic extraction either as harmonic oscillators or as frequency multipliers. We augment the traditional maximum oscillation frequency metric (fmax), which only accounts for transistor losses, with passive component loss to derive an effective fmax metric. We then present a methodology for building oscillators at this fmax, the Maximum Gain Ring Oscillator. Next, we explore generating large signals beyond fmax through harmonic extraction in multipliers. Applying concepts of waveform shaping, we demonstrate a Power Mixer that engineers transistor nonlinearity by manipulating the amplitudes and relative phase shifts of different device nodes to maximize performance at a specific harmonic beyond device cut-off.
The second half proposes a new architecture for an ultra-low noise phase-locked loop (PLL), the Reference-Sampling PLL. In conventional PLLs, a noisy buffer converts the slow, low-noise sine-wave reference signal to a jittery square-wave clock against which the phase of a noisy voltage-controlled oscillator (VCO) is corrected. We eliminate this reference buffer, and measure phase error by sampling the reference sine-wave with the 50x faster VCO waveform already available on chip, and selecting the relevant sample with voltage proportional to phase error. By avoiding the N-squared multiplication of the high-power reference buffer noise, and directly using voltage-mode phase error to control the VCO, we eliminate several noisy components in the controlling loop for ultra-low integrated jitter for a given power consumption. Further, isolation of the VCO tank from any varying load, unlike other contemporary divider-less PLL architectures, results in an architecture with record performance in the low-noise and low-spur space.
We conclude with work that brings together concepts developed for clean, high-power signal generation towards a hybrid CMOS-Optical approach to Frequency-Modulated Continuous-Wave (FMCW) Light-Detection-And-Ranging (LIDAR). Cost-effective tunable lasers are temperature-sensitive and have nonlinear tuning profiles, rendering precise frequency modulations or 'chirps' untenable. Locking them to an electronic reference through an electro-optic PLL, and electronically calibrating the control signal for nonlinearity and ambient sensitivity, can make such chirps possible. Approaches that build on the body of advances in electrical PLLs to control the performance, and ease the specification on the design of optical systems are proposed. Eventually, we seek to leverage the twin advantages of silicon-intensive integration and low-cost high-yield towards developing a single-chip solution that uses on-chip signal processing and phased arrays to generate precise and robust chirps for an electronically-steerable fine LIDAR beam
One way Doppler extractor. Volume 1: Vernier technique
A feasibility analysis, trade-offs, and implementation for a One Way Doppler Extraction system are discussed. A Doppler error analysis shows that quantization error is a primary source of Doppler measurement error. Several competing extraction techniques are compared and a Vernier technique is developed which obtains high Doppler resolution with low speed logic. Parameter trade-offs and sensitivities for the Vernier technique are analyzed, leading to a hardware design configuration. A detailed design, operation, and performance evaluation of the resulting breadboard model is presented which verifies the theoretical performance predictions. Performance tests have verified that the breadboard is capable of extracting Doppler, on an S-band signal, to an accuracy of less than 0.02 Hertz for a one second averaging period. This corresponds to a range rate error of no more than 3 millimeters per second
SiGe based multiple-phase VCO operating for mm-wave frequencies
The ever-increasing demand for higher speed in wireless consumer applications has increased the interest in the unlicensed spectrum of 7 GHz around 60 GHz. The high atmospheric oxygen absorption at 60 GHz and small size of the antennas at this frequency requires the use of integrated phased-array systems to overcome the deficiencies of lossy channels at these frequencies. The phased arrays combine signals from multiple paths to obtain higher receiver sensitivity and directivity. The system thus requires phase-shifted voltage-controlled oscillator (VCO) signals to implement phase shifting in the local-oscillator (LO) path. In this research, the vector sum method to generate various phases of the signal at 60 GHz was investigated for its suitability in phased-array systems. The main focus was on improving the phase noise performance of the VCO. The VCO was implemented using a fully differential common-collector Colpitts oscillator in the cascode configuration, which was found to be the VCO configuration with acceptable phase noise performance and stability in the millimetre-wave range. The research focus was on modelling the phase noise of the VCO, and was performed by identifying the impulse sensitivity function for various noise sources, followed by analysing its effect on the linear time varying (LTV) model of the oscillators. The analysis led to a closed-form expression for the phase noise of the oscillator in terms of process and design parameters. The design was then optimised in terms of identified parameters to attain minimum phase noise. The phase noise expression using LTV theory and SpectreRF simulations reported the same optimum value for the design parameter, of around 0.3 for the capacitor ratio. The simulation results utilising the vector sum phase shifting method to generate multiple phase oscillator signals suggest its suitability in implementing phased-array systems in the millimetre-wave range. The vector sum was realised by generating quadrature signals from the oscillator using hybrid couplers. Variable gain amplifiers (VGAs) based on Gilbert mixer topology were used to combine the in-phase and quadrature phase signals to generate the phase-shifted oscillator signal. The gains of the VGAs were linearised by using a pre-distortion circuit, which was an inverse tanh cell. A fully differential 60 GHz VCO was fabricated using a SiGe process with a fT of 200 GHz. The fabricated integrated circuit (IC) measured at the wafer level had a centre frequency of 52.8 GHz and a tuning range of 7 GHz. It demonstrated a phase noise performance of -98.9 dBc/Hz at 1 MHz offset and a power dissipation of 140 mW, thus providing a VCO figure of merit of 172 dBc/Hz. It delivered a differential output power of 8 dBm and the IC occupied an area of 0.54 mm2, including the bondpads. It was thus concluded that a 10 % design margin for the tuning range is required while using SiGe BiCMOS technology. The simulation results demonstrate that the VCO, along with an active interpolator, provides a range of phase-shifted signals from 0° to 360° in steps of 22.5° for various gain settings of the VGAs. The power dissipation of the active interpolator is around 60 mW and the system could thus be employed in LO path shifting architecture of the phased arrays with increased power consumption.Thesis (PhD)--University of Pretoria, 2013.Electrical, Electronic and Computer Engineeringunrestricte
Analysis and Design of a Sub-THz Ultra-Wideband Phased-Array Transmitter
This thesis investigates circuits and systems for broadband high datarate transmitter systems in the millimeter-wave (mm-wave) spectrum. During the course of this dissertation, the design process and characterization of a power efficient and wideband binary phase-shift keying (BPSK) transmitter integrated circuit (IC) with local oscillator (LO) frequency multiplication and 360° phase control for beam steering is studied. All required circuit blocks are designed based on the theoretical analysis of the underlying principles, optimized, fabricated and characterized in the research laboratory targeting low power consumption, high efficiency and broadband operation. The phase-controlled push-push (PCPP) architecture enabling frequency multiplication by four in a single stage is analytically studied and characterized finding an optimum between output power and second harmonic suppression depending on the input amplitude. A PCPP based LO chain is designed. A circuit is fabricated establishing the feasibility of this architecture for operation at more than 200 GHz. Building on this, a second circuit is designed, which produces among the highest saturated output powers at 2 dBm. At less than 100 mW of direct current (DC) power consumption, this results in a power-added efficiency (PAE) of 1.6 % improving the state of the art by almost 30 %. Phase-delayed and time-delayed approaches to beam steering are analyzed, identifying and discussing design challenges like area consumption, signal attenuation and beam squint. A 60 GHz active vector-sum phase-shifter with high gain of 11.3 dB and output power of 5 dBm, improving the PAE of the state of the art by a factor of 30 achieving 6.29 %, is designed. The high gain is possible due to an optimization of the orthogonal signal creation stage enabled by studying and comparing different architectures leading to a trade off of lower signal attenuation for higher area consumption in the chosen electromagnetic coupler. By combining this with a frequency quadrupler, a phase steering enabled LO chain for operation at 220 GHz is created and characterized, confirming the preceding analysis of the phase-frequency relation during multiplication. It achieves a power gain of 21 dB, outperforming comparable designs by 25 dB. This allows the combination of phase control, frequency multiplication and pre-amplification. The radio frequency (RF) efficiency is increased 40-fold to 0.99 %, with a total power consumption of 105 mW. Motivated by the distorting effect of beam squint in phase-delayed broadband array systems, a novel analog hybrid beam steering architecture is devised, combining phase-delayed and time-delayed steering with the goal of reducing the beam squint of phase-delayed systems and large area consumption of time-delayed circuits. An analytical design procedure is presented leading to the research finding of a beam squint reduction potential of more than 83 % in an ideal system. Here, the increase in area consumption is outweighed by the reduction in beam squint. An IC with a low power consumption of 4.3 mW has been fabricated and characterized featuring the first time delay circuit operating at above 200 GHz. By producing most of the beam direction by means of time delay the beam squinting can be reduced by more than 75 % in measurements while the subsequent phase shifter ensures continuous beam direction control. Together, the required silicon area can be reduced to 43 % compared to timedelayed systems in the same frequency range. Based on studies of the optimum signal feeding and input matching of a Gilbert cell, an ultra-wideband, low-power mixer was designed. A bandwidth of more than 100 GHz was achieved exceeding the state of the art by 23 %. With a conversion gain of –13 dB, this enables datarates of more than 100 Gbps in BPSK operation. The findings are consolidated in an integrated transmitter operating around 246 GHz doubling the highest published measured datarates of transmitters with LO chain and power amplifier in BPSK operation to 56 Gbps. The resulting transmitter efficiency of 7.4 pJ/bit improves the state of the art by 70 % and 50 % over BPSK and quadrature phaseshift keying (QPSK) systems, respectively. Together, the results of this work form the basis for low-power and efficient next-generation wireless applications operating at many times the datarates available today.:Abstract 3
Zusammenfassung 5
List of Symbols 11
List of Acronyms 17
Prior Publications 19
1. Introduction 21
1.1. Motivation........................... 21
1.2. Objective of this Thesis ................... 25
1.3. Structure of this Thesis ................... 27
2. Overview of Employed Technologies and Techniques 29
2.1. IntegratedCircuitTechnology................ 29
2.2. Transmission Lines and Passive Structures . . . . . . . . 35
2.3. DigitalModulation ...................... 41
3. Frequency Quadrupler 45
3.1. Theoretical Analysis of Frequency Multiplication Circuits 45
3.2. Phase-Controlled Push-Push Principle for Frequency
Quadrupling.......................... 49
3.3. Stand-alone Phase-Controlled Push-Push Quadrupler . 60
3.4. Phase-Controlled Push-Push Quadrupler based LO-chain with High Output Power ............... 72 9
4. Array Systems and Dynamic Beam Steering 91
4.1. Theoretical Analysis of BeamSteering. . . . . . . . . . . 95
4.2. Local Oscillator Phase Shifting with Vector-Modulator PhaseShifters......................... 107
4.3. Hybrid True-Time and Phase-Delayed Beam Steering . 131
5. Ultra-Wide Band Modulator for BPSK Operation 155
6. Broadband BPSK Transmitter System for Datarates up to 56 Gbps 167
6.1. System Architecture ..................... 168
6.2. Measurement Technique and Results . . . . . . . . . . . 171
6.3. Summary and performance comparison . . . . . . . . . 185
7. Conclusion and Outlook 189
A. Appendix 195
Bibliography 199
List of Figures 227
Note of Thanks 239
Curriculum Vitae 241Diese Dissertation untersucht Schaltungen und Systeme für breitbandige Transmittersysteme mit hoher Datenrate im Millimeterwellen (mm-wave) Spektrum. Im Rahmen dieser Arbeit werden der Entwurfsprozess und die Charakterisierung eines leistungseffizienten und breitbandigen integrierten Senders basierend auf binärer Phasenumtastung (BPSK) mit Frequenzvervielfachung des Lokaloszillatorsignals und 360°-Phasenkontrolle zur Strahlsteuerung untersucht. Alle erforderlichen Schaltungsblöcke werden auf Grundlage von theoretischen Analysen der zugrundeliegenden Prinzipien entworfen, optimiert, hergestellt und im Forschungslabor charakterisiert, mit den Zielen einer niedrigen Leistungsaufnahme, eines hohen Wirkungsgrades und einer möglichst großen Bandbreite. Die phasengesteuerte Push-Push (PCPP)-Architektur, welche eine Frequenzvervierfachung in einer einzigen Stufe ermöglicht, wird analytisch untersucht und charakterisiert. Dabei wird ein Optimum zwischen Ausgangsleistung und Unterdrückung der zweiten Harmonischen des Eingangssignals in Abhängigkeit von der Eingangsamplitude gefunden. Es wird eine LO-Kette auf PCPP-Basis entworfen. Eine Schaltung wird präsentiert, die die Machbarkeit dieser Architektur für den Betrieb bei mehr als 200 GHz nachweist. Darauf aufbauend wird eine zweite Schaltung entworfen, die mit 2 dBm eine der höchsten publizierten gesättigten Ausgangsleistungen erzeugt. Mit einer Leistungsaufnahme von weniger als 100mW ergibt sich ein Leistungswirkungsgrad (PAE) von 1.6 %, was den Stand der Technik um fast 30 % verbessert. Es werden phasenverzögerte und zeitverzögerte Ansätze zur Steuerung der Strahlrichtung analysiert, wobei Entwicklungsherausforderungen wie Flächenverbrauch, Signaldämpfung und Strahlschielen identifiziert und diskutiert werden. Ein aktiver Vektorsummen-Phasenschieber mit hoher Verstärkung von 11.3 dB und einer Ausgangsleistung von 5 dBm, der mit einer PAE von 6.29 % den Stand der Technik um den Faktor 30 verbessert, wird entworfen. Die hohe Verstärkung ist zum Teil auf eine Optimierung der orthogonalen Signalerzeugungsstufe zurückzuführen, die durch die Untersuchung und den Vergleich verschiedener Architekturen ermöglicht wird. Bei der Entscheidung für einen elektromagnetischen Koppler rechtfertigt die geringere Signaldämpfung einen höheren Flächenverbrauch. Durch die Kombination mit einem Frequenzvervierfacher wird eine LO-Kette mit Phasensteuerung für den Betrieb bei 220 GHz geschaffen und charakterisiert, was die vorangegangene Analyse der Phasen-FrequenzBeziehung während der Multiplikation bestätigt. Sie erreicht einen Leistungsgewinn von 21 dB und übertrifft damit vergleichbare Designs um 25dB. Dies ermöglicht die Kombination von Phasensteuerung, Frequenzvervielfachung und Vorverstärkung. Der HochfrequenzWirkungsgrad wird um das 40-fache auf 0.99 % bei einer Gesamtleistungsaufnahme von 105 mW gesteigert. Motiviert durch den verzerrenden Effekt des Strahlenschielens in phasengesteuerten Breitbandarraysystemen, wird eine neuartige analoge hybride Strahlsteuerungsarchitektur untersucht, die phasenverzögerte und zeitverzögerte Steuerung kombiniert. Damit wird sowohl das Strahlenschielen phasenverzögerter Systeme als auch der große Flächenverbrauch zeitverzögerter Schaltungen reduziert. Es wird ein analytisches Entwurfsverfahren vorgestellt, das zu dem Forschungsergebnis führt, dass in einem idealen System ein Potenzial zur Reduktion des Strahlenschielens von mehr als 83 % besteht. Dabei wird die Zunahme des Flächenverbrauchs durch die Verringerung des Strahlenschielens aufgewogen. Es wird ein IC mit einer geringen Leistungsaufnahme von 4.3mW hergestellt und charakterisiert. Dabei wird die erste Zeitverzögerungsschaltung entworfen, die bei über 200 GHz arbeitet. Durch die Erzeugung eines Großteils der Strahlrichtung mittels Zeitverzögerung kann das Schielen des Strahls bei Messungen um mehr als 75% reduziert werden, während der nachfolgende Phasenschieber eine kontinuierliche Steuerung der Strahlrichtung gewährleistet. Insgesamt kann die benötigte Siliziumfläche im Vergleich zu zeitverzögerten Systemen im gleichen Frequenzbereich auf 43 % reduziert werden. Auf der Grundlage von Studien zur optimalen Signaleinspeisung und Eingangsanpassung einer Gilbert-Zelle wird ein Ultrabreitband-Mischer mit geringem Stromverbrauch entworfen. Dieser erreicht eine Ausgangsbandbreite von mehr als 100 GHz, die den Stand der Technik um 23% übertrifft. Bei einer Wandlungsverstärkung von –13dB ermöglicht dies Datenraten von mehr als 100 Gbps im BPSK-Betrieb. Die Erkenntnisse werden in einem integrierten, breitbandigen Sender konsolidiert, der um 246 GHz arbeitet und die höchsten veröffentlichten gemessenen Datenraten für Sender mit LO-Signalkette und Leistungsverstärker im BPSK-Betrieb auf 56 Gbps verdoppelt. Die daraus resultierende Transmitter-Effizienz von 7.4 pJ/bit verbessert den Stand der Technik um 70 % bzw. 50 % gegenüber BPSKund Quadratur Phasenumtastung (QPSK)-Systemen. Zusammen bilden die Ergebnisse dieser Arbeit die Grundlage für stromsparende, effiziente, mobile Funkanwendungen der nächsten Generation mit einem Vielfachen der heute verfügbaren Datenraten.:Abstract 3
Zusammenfassung 5
List of Symbols 11
List of Acronyms 17
Prior Publications 19
1. Introduction 21
1.1. Motivation........................... 21
1.2. Objective of this Thesis ................... 25
1.3. Structure of this Thesis ................... 27
2. Overview of Employed Technologies and Techniques 29
2.1. IntegratedCircuitTechnology................ 29
2.2. Transmission Lines and Passive Structures . . . . . . . . 35
2.3. DigitalModulation ...................... 41
3. Frequency Quadrupler 45
3.1. Theoretical Analysis of Frequency Multiplication Circuits 45
3.2. Phase-Controlled Push-Push Principle for Frequency
Quadrupling.......................... 49
3.3. Stand-alone Phase-Controlled Push-Push Quadrupler . 60
3.4. Phase-Controlled Push-Push Quadrupler based LO-chain with High Output Power ............... 72 9
4. Array Systems and Dynamic Beam Steering 91
4.1. Theoretical Analysis of BeamSteering. . . . . . . . . . . 95
4.2. Local Oscillator Phase Shifting with Vector-Modulator PhaseShifters......................... 107
4.3. Hybrid True-Time and Phase-Delayed Beam Steering . 131
5. Ultra-Wide Band Modulator for BPSK Operation 155
6. Broadband BPSK Transmitter System for Datarates up to 56 Gbps 167
6.1. System Architecture ..................... 168
6.2. Measurement Technique and Results . . . . . . . . . . . 171
6.3. Summary and performance comparison . . . . . . . . . 185
7. Conclusion and Outlook 189
A. Appendix 195
Bibliography 199
List of Figures 227
Note of Thanks 239
Curriculum Vitae 24
Circuit Design Techniques For Wideband Phased Arrays
University of Minnesota Ph.D. dissertation.June 2015. Major: Electrical Engineering. Advisor: Ramesh Harjani. 1 computer file (PDF); xii, 143 pages.This dissertation focuses on beam steering in wideband phased arrays and phase noise modeling in injection locked oscillators. Two different solutions, one in frequency and one in time, have been proposed to minimize beam squinting in phased arrays. Additionally, a differential current reuse frequency doubler for area and power savings has been proposed. Silicon measurement results are provided for the frequency domain solution (IBM 65nm RF CMOS), injection locked oscillator model verification (IBM 130nm RF-CMOS) and frequency doubler (IBM 65nm RF CMOS), while post extraction simulation results are provided for the time domain phased array solution (the chip is currently under fabrication, TSMC 65nm RF CMOS). In the frequency domain solution, a 4-point passive analog FFT based frequency tunable filter is used to channelize an incoming wideband signal into multiple narrowband signals, which are then processed through independent phase shifters. A two channel prototype has been developed at 8GHz RF frequency. Three discrete phase shifts (0 & +/- 90 degrees) are implemented through differential I-Q swapping with appropriate polarity. A minimum null-depth of 19dB while a maximum null-depth of 27dB is measured. In the time domain solution, a discrete time approach is undertaken with signals getting sampled in order of their arrival times. A two-channel prototype for a 2GHz instantaneous RF bandwidth (7GHz-9GHz) has been designed. A QVCO generates quadrature LO signals at 8GHz which are phase shifted through a 5-bit (2 extra bits from differential I-Q swapping with appropriate polarity) cartesian combiner. Baseband sampling clocks are generated from phase shifted LOs through a CMOS divide by 4 with independent resets. The design achieves an average time delay of 4.53ps with 31.5mW of power consumption (per channel, buffers excluded). An injection locked oscillator has been analyzed in s-domain using Paciorek's time domain transient equations. The simplified analysis leads to a phase noise model identical to that of a type-I PLL. The model is equally applicable to injection locked dividers and multipliers and has been extended to cover all injection locking scenarios. The model has been verified against a discrete 57MHz Colpitt's ILO, a 6.5GHz ILFD and a 24GHz ILFM with excellent matching between the model and measurements. Additionally, a differential current reuse frequency doubler, for frequency outputs between 7GHz to 14GHz, design has been developed to reduce passive area and dc power dissipation. A 3-bit capacitive tuning along with a tail current source is used to better conversion efficiency. The doubler shows FOM values between 191dBc/Hz to 209dBc/Hz when driven by a 0.7GHz to 5.8GHz wide tuning VCO with a phase noise that ranges from -114dBc/Hz to -112dBc/Hz over the same bandwidth
Passive and active circuits in cmos technology for rf, microwave and millimeter wave applications
The permeation of CMOS technology to radio frequencies and beyond has
fuelled an urgent need for a diverse array of passive and active circuits that address the
challenges of rapidly emerging wireless applications. While traditional analog based
design approaches satisfy some applications, the stringent requirements of newly
emerging applications cannot necessarily be addressed by existing design ideas and
compel designers to pursue alternatives. One such alternative, an amalgamation of
microwave and analog design techniques, is pursued in this work.
A number of passive and active circuits have been designed using a combination
of microwave and analog design techniques. For passives, the most crucial challenge to
their CMOS implementation is identified as their large dimensions that are not
compatible with CMOS technology. To address this issue, several design techniques –
including multi-layered design and slow wave structures – are proposed and
demonstrated through experimental results after being suitably tailored for CMOS
technology. A number of novel passive structures - including a compact 10 GHz hairpin resonator, a broadband, low loss 25-35 GHz Lange coupler, a 25-35 GHz thin film
microstrip (TFMS) ring hybrid, an array of 0.8 nH and 0.4 nH multi-layered high self
resonant frequency (SRF) inductors are proposed, designed and experimentally verified.
A number of active circuits are also designed and notable experimental results
are presented. These include 3-10 GHz and DC-20 GHz distributed low noise amplifiers
(LNA), a dual wideband Low noise amplifier and 15 GHz distributed voltage controlled
oscillators (DVCO). Distributed amplifiers are identified as particularly effective in the
development of wideband receiver front end sub-systems due to their gain flatness,
excellent matching and high linearity. The most important challenge to the
implementation of distributed amplifiers in CMOS RFICs is identified as the issue of
their miniaturization. This problem is solved by using integrated multi-layered inductors
instead of transmission lines to achieve over 90% size compression compared to earlier
CMOS implementations. Finally, a dual wideband receiver front end sub-system is
designed employing the miniaturized distributed amplifier with resonant loads and
integrated with a double balanced Gilbert cell mixer to perform dual band operation. The
receiver front end measured results show 15 dB conversion gain, and a 1-dB
compression point of -4.1 dBm in the centre of band 1 (from 3.1 to 5.0 GHz) and -5.2
dBm in the centre of band 2 (from 5.8 to 8 GHz) with input return loss less than 10 dB
throughout the two bands of operation
SiGe BiCMOS RF front-ends for adaptive wideband receivers
The pursuit of dense monolithic integration and higher operating speed continues to push the integrated circuit (IC) fabrication technologies to their limits. The increasing process variation, associated with aggressive technology scaling, is having a negative impact on circuit yield in current IC technologies, and the problem is likely to become worse in the future. Circuit solutions that are more tolerant of the process variations are needed to fully utilize the benefits of technology scaling. The primary goal of this research is to develop high-frequency circuits that can deliver consistent performance even under the threat of increasing process variation. These circuits can be used to build ``self-healing" systems, which can detect process imperfections and compensate accordingly to optimize performance. In addition to improving yield, such adaptive circuits and systems can provide more robust and efficient solutions for a wide range of applications under varying operational and environmental conditions.Silicon-germanium (SiGe) BiCMOS technology is an ideal platform for highly integrated systems requiring both high-performance analog and radio-frequency (RF) circuits as well as large-scale digital functionality. This research is focused on designing circuit components for a high-frequency wideband self-healing receiver in SiGe BiCMOS technology. An adaptive image-reject mixer, low insertion-loss switches, a wideband low-noise amplifier (LNA), and a SiGe complementary LC oscillator were designed. Healing algorithms were developed, and automated self-healing of multiple parameters of the mixer was demonstrated in measurement. A monte-carlo simulation based methodology was developed to verify the effectiveness of the healing procedure. In summary, this research developed circuits, algorithms, simulation tools, and methods that are useful for building "self-healing" systems.Ph.D
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High Performance Local Oscillator Design for Next Generation Wireless Communication
Local Oscillator (LO) is an essential building block in modern wireless radios. In modern wireless radios, LO often serves as a reference of the carrier signal to modulate or demod- ulate the outgoing or incoming data. The LO signal should be a clean and stable source, such that the frequency or timing information of the carrier reference can be well-defined. However, as radio architecture evolves, the importance of LO path design has become much more important than before. Of late, many radio architecture innovations have exploited sophisticated LO generation schemes to meet the ever-increasing demands of wireless radio performances.
The focus of this thesis is to address challenges in the LO path design for next-generation high performance wireless radios. These challenges include (1) Congested spectrum at low radio frequency (RF) below 5GHz (2) Continuing miniaturization of integrated wireless radio, and (3) Fiber-fast (>10Gb/s) mm-wave wireless communication.
The thesis begins with a brief introduction of the aforementioned challenges followed by a discussion of the opportunities projected to overcome these challenges.
To address the challenge of congested spectrum at frequency below 5GHz, novel ra- dio architectures such as cognitive radio, software-defined radio, and full-duplex radio have drawn significant research interest. Cognitive radio is a radio architecture that opportunisti- cally utilize the unused spectrum in an environment to maximize spectrum usage efficiency. Energy-efficient spectrum sensing is the key to implementing cognitive radio. To enable energy-efficient spectrum sensing, a fast-hopping frequency synthesizer is an essential build- ing block to swiftly sweep the carrier frequency of the radio across the available spectrum. Chapter 2 of this thesis further highlights the challenges and trade-offs of the current LO gen-
eration scheme for possible use in sweeping LO-based spectrum analysis. It follows by intro- duction of the proposed fast-hopping LO architecture, its implementation and measurement results of the validated prototype. Chapter 3 proposes an embedded phase-shifting LO-path design for wideband RF self-interference cancellation for full-duplex radio. It demonstrates a synergistic design between the LO path and signal to perform self-interference cancellation.
To address the challenge of continuing miniaturization of integrated wireless radio, ring oscillator-based frequency synthesizer is an attractive candidate due to its compactness. Chapter 4 discussed the difficulty associated with implementing a Phase-Locked Loop (PLL) with ultra-small form-factor. It further proposes the concept sub-sampling PLL with time- based loop filter to address these challenges. A 65nm CMOS prototype and its measurement result are presented for validation of the concept.
In shifting from RF to mm-wave frequencies, the performance of wireless communication links is boosted by significant bandwidth and data-rate expansion. However, the demand for data-rate improvement is out-pacing the innovation of radio architectures. A >10Gb/s mm-wave wireless communication at 60GHz is required by emerging applications such as virtual-reality (VR) headsets, inter-rack data transmission at data center, and Ultra-High- Definition (UHD) TV home entertainment systems. Channel-bonding is considered to be a promising technique for achieving >10Gb/s wireless communication at 60GHz. Chapter 5 discusses the fundamental radio implementation challenges associated with channel-bonding for 60GHz wireless communication and the pros and cons of prior arts that attempted to address these challenges. It is followed by a discussion of the proposed 60GHz channel- bonding receiver, which utilizes only a single PLL and enables both contiguous and non- contiguous channel-bonding schemes.
Finally, Chapter 6 presents the conclusion of this thesis
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