Evolution of digitally controlled oscillator

Suvremeni razvoj uporabe digitalnih ili potpuno digitalnih ciklusa s faznim podešavanjem (PLLs) u različitim uređajima za komunikaciju vodi ka primjeni digitalno kontroliranog oscilatora (DCO). U ovom se preglednom članku daje razvoj DCO-a u modernim elektroničkim uređajima kao i njihovo funkcioniranje u lokalnim oscilatorima. Iako se implementacija DCO preferira u odnosu na analogne, i dalje se radi na poboljšanjima u potrošnji energije, brzini, veličini čipa, raspona frekvencije, ulaznog napona, prenosivosti i rezolucije. U radu se uglavnom opisuje razvoj od oscilatora kontroliranih voltažom (voltage controlled oscillators- VCO) do digitalno kontroliranih oscilatora za "deep-submicrometer CMOS" postupak. Fokus je na analizi i praćenju unapređenja DCO-a na razini funkcionalnosti.Current trend of using digital or all-digital phase-locked loops (PLLs) in various communication devices introduces the usage of digitally controlled oscillator (DCO). This review paper discusses the evolution of DCOs in modern electronic devices as well as their performances in local oscillators. Even though the DCO implementation is preferable to its analog counterpart, improvements are still going on to get high performances in terms of power consumption, speed, chip area, frequency range, supply voltage, portability and resolution. This paper mainly describes the evolution of DCO, how it turns from a conventional VCO to DCO for deep-submicrometer CMOS process. The focus is to analyse and track the advances in DCO base on its performance level

Evolution of digitally controlled oscillator

Suvremeni razvoj uporabe digitalnih ili potpuno digitalnih ciklusa s faznim podešavanjem (PLLs) u različitim uređajima za komunikaciju vodi ka primjeni digitalno kontroliranog oscilatora (DCO). U ovom se preglednom članku daje razvoj DCO-a u modernim elektroničkim uređajima kao i njihovo funkcioniranje u lokalnim oscilatorima. Iako se implementacija DCO preferira u odnosu na analogne, i dalje se radi na poboljšanjima u potrošnji energije, brzini, veličini čipa, raspona frekvencije, ulaznog napona, prenosivosti i rezolucije. U radu se uglavnom opisuje razvoj od oscilatora kontroliranih voltažom (voltage controlled oscillators- VCO) do digitalno kontroliranih oscilatora za "deep-submicrometer CMOS" postupak. Fokus je na analizi i praćenju unapređenja DCO-a na razini funkcionalnosti.Current trend of using digital or all-digital phase-locked loops (PLLs) in various communication devices introduces the usage of digitally controlled oscillator (DCO). This review paper discusses the evolution of DCOs in modern electronic devices as well as their performances in local oscillators. Even though the DCO implementation is preferable to its analog counterpart, improvements are still going on to get high performances in terms of power consumption, speed, chip area, frequency range, supply voltage, portability and resolution. This paper mainly describes the evolution of DCO, how it turns from a conventional VCO to DCO for deep-submicrometer CMOS process. The focus is to analyse and track the advances in DCO base on its performance level

Quadrature Phase-Domain ADPLL with Integrated On-line Amplitude Locked Loop Calibration for 5G Multi-band Applications

5th generation wireless systems (5G) have expanded frequency band coverage with the low-band 5G and mid-band 5G frequencies spanning 600 MHz to 4 GHz spectrum. This dissertation focuses on a microelectronic implementation of CMOS 65 nm design of an All-Digital Phase Lock Loop (ADPLL), which is a critical component for advanced 5G wireless transceivers. The ADPLL is designed to operate in the frequency bands of 600MHz-930MHz, 2.4GHz-2.8GHz and 3.4GHz-4.2GHz. Unique ADPLL sub-components include: 1) Digital Phase Frequency Detector, 2) Digital Loop Filter, 3) Channel Bank Select Circuit, and 4) Digital Control Oscillator. Integrated with the ADPLL is a 90-degree active RC-CR phase shifter with on-line amplitude locked loop (ALL) calibration to facilitate enhanced image rejection while mitigating the effects of fabrication process variations and component mismatch. A unique high-sensitivity high-speed dynamic voltage comparator is included as a key component of the active phase shifter/ALL calibration subsystem. 65nm CMOS technology circuit designs are included for the ADPLL and active phase shifter with simulation performance assessments. Phase noise results for 1 MHz offset with carrier frequencies of 600MHz, 2.4GHz, and 3.8GHz are -130, -122, and -116 dBc/Hz, respectively. Monte Carlo simulations to account for process variations/component mismatch show that the active phase shifter with ALL calibration maintains accurate quadrature phase outputs when operating within the frequency bands 600MHz-930MHz, 2.4GHz-2.8GHz and 3.4GHz-4.2GHz

An all-digital transmitter for pulsed ultra-wideband communication

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (p. 91-96).Applications like sensor networks, medical monitoring, and asset tracking have led to a demand for energy-efficient and low-cost wireless transceivers. These types of applications typically require low effective data rates, thus providing an opportunity to employ simple modulation schemes and aggressive duty-cycling. Due to their inherently duty-cycled nature, pulse-based Ultra-Wideband (UWB) systems are amenable to low-power operation by shutting off circuitry during idle mode between pulses. Furthermore, the use of non-coherent UWB signaling greatly simplifies both transmitter and receiver implementations, offering additional energy savings. This thesis presents an all-digital transmitter designed for a non-coherent pulsed UWB system. By exploiting relaxed center frequency tolerances in non-coherent wideband communication, the transmitter synthesizes UWB pulses from an energy efficient, single-ended digital ring oscillator. Dual capacitively-coupled digital power amplifiers (PAs) are used in tandem to generate bipolar phase modulated pulses for spectral scrambling purposes. By maintaining opposite common modes at the output of these PAs during idle mode (i.e. when no pulses are being transmitted), low frequency turn-on and turn-off transients typically associated with single-ended digital circuits driving single-ended antennas are attenuated by up to 12dB. Furthermore, four level digital pulse shaping is employed to attenuate RF side lobes by up to 20dB. The resulting dual power amplifiers achieve FCC compliant operation in the 3.5, 4.0, and 4.5GHz IEEE 802.15.4a bands without the use of any off-chip filters or large passive components. The transmitter is fabricated in a 90nm CMOS process and requires a core area of 0.07mm2. The entirely digital architecture consumes zero static bias current, resulting in an energy efficiency of 17.5pJ/pulse at data rates up to 15.6Mbps.by Patrick Philip Mercier.S.M