Analysis of the subthreshold current of pocket or halo-implanted nMOSFETs

In this work, we analyzed the subthreshold current (I/sub D/) of pocket implanted MOSFETs using extensive device simulations and experimental data. We present an analytical model for the subthreshold current applicable for any type of FET and show that the subthreshold current of nMOSFETs, which is mainly due to diffusion, is determined by the internal two-dimensional hole distribution across the device. This hole distribution is affected by the electric potential of the gate and the doping concentration in the channel. The results obtained allow accurate modelling of the subthreshold current of future generation MOS devices

The operational characteristics and potential applications of a low voltage EMCCD in a CMOS process

The Electron Multiplying Test Chip 1 (EMTC1) was developed with the aim of creating a device which could produce superior Electron Multiplication (EM) gain at a greatly reduced voltage. An EM gain exceeding 3% per stage has been recorded for a relatively low voltage (~13.0V) from two recently developed pixel structures. An electro-optical characterisation of the EMTC1 is presented focusing on charge transfer via experimental and simulation results aiming to provide insight into the transfer and multiplication process. The Charge Transfer Inefficiency (CTI) is analysed with the aim of providing a greater understanding of the charge transfer process. Light starved applications such as Earth observation and automated inspection are known to benefit from Time Delay Integration (TDI) and electron multiplication. Though traditionally implemented in CCDs, implementing TDI in CMOS technology can lead to an increase of functionality, higher readout speeds and reduced noise. This paper presents a discussion of the implication of these results on the potential applications of this sensor

Comparison analysis on scaling the vertical and lateral NMOSFET in nanometer regime

Conventional lateral and vertical n-channel MOS transistors with channel length in the range of 100 nm to 50 nm have been systematically investigated by means of device simulation. The comparison analysis includes critical parameters that govern device performance. Threshold voltage VT roll-off, leakage current Ioff drain saturation current IDsat and sub-threshold swing S were analyze and compared between the device. Due to double gate (DG) structure over the side of silicon pillar a better electrostatics potential control of channel is obtained in vertical device shown by an analysis on VT roll-off. A two decade higher of Ioff in planar device is observed with Lg = 50 nm. A factor of three times larger IDsat is observed for vertical MOSFETs compared to planar device. The sub-threshold swing S remains almost the same when the Lg larger than 80 nm. It increased rapidly when the Lg is scaled down to 50 nm due to the short channel effect SCE. However, the vertical device has a steady increase whereas the planar device has suffered immediate enhance of SCE. The analysis results confirmed that vertical MOSFET with double-gate structure is a potential solution to overcome SCE when scaled the channel length to 50 nm and beyond

Experimental and simulation study of 1D silicon nanowire transistors using heavily doped channels

The experimental results from 8 nm diameter silicon nanowire junctionless field effect transistors with gate lengths of 150 nm are presented that demonstrate on-currents up to 1.15 mA/m for 1.0 V and 2.52 mA/m for 1.8 V gate overdrive with an off-current set at 100 nA/m. On- to off-current ratios above 108 with a subthreshold slope of 66 mV/dec are demonstrated at 25 oC. Simulations using drift-diffusion which include densitygradient quantum corrections provide excellent agreement with the experimental results. The simulations demonstrate that the present silicon-dioxide gate dielectric only allows the gate to be scaled to 25 nm length before short-channel effects significantly reduce the performance. If high-K dielectrics replace some parts of the silicon dioxide then the technology can be scaled to at least 10 nm gatelength

On the numerical modeling of terahertz photoconductive antennas

This paper shows the relevance of mobility models to describe the car- rier dynamics for the analysis of radiative semiconductor photoconductive devices in the terahertz regime. We have built a simulator that self-consistently solves the device physics and Maxwell’s equations to study the radiated fields. In particu- lar, we show a significant influence of an accurate description of the steady-state regime of the semiconductor device for calculating radiated electromagnetic fields in the broadside direction. Comparison with measurements shows the accuracy of our simulator and demonstrates the superior performance of numerical schemes based not only on the description of the carrier, electric potential, and field dis- tributions, but also on reliable local mobility models.This work was supported in part by the Spanish Ministry of Educa- tion under Project CSD2008-00068, the Junta de Andalucia Project P09-TIC-5327, the EU FP7/2007-2013, under grant 205294 (HIRF-SE project), and the Spanish National Project TEC2010-20841-C04-04

Structure Oriented Compact Model for Advanced Trench IGBTs without Fitting Parameters for Extreme Condition: part I

2011 22nd European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, ESREF 2011, Oct 3-7, 2011, Universit Bordeaux 1, Domaine Haut Carr, Agora Talence, FranceA device structure based compact model for advanced trench gate IGBTs is proposed. The model is formulated only with device structure parameters so that no fitting parameters are required. The model is applicable to extreme conditions such as under very low or high temperatures. The validity of the model formulation is confirmed with two-dimensional TCAD simulation for voltage range of 1.2kV and 3.3kV IGBTs, and for temperature range of 300K and 450K. In this paper conduction mode formulation is proposed which has the potential to be used for system level failure analysis

Study of Electron Transport in Fullerene (C60) Quantum Confined Channel Layer Based Field Effect Transistor

In this work, we modelled a simple n-channel Si Metal-Quantum confined layer-Semiconductor Field Effect Transistor (MQSFET), which resembles exactly as the conventional Si Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) where SiO2 dielectric layer is replaced with a wide band gap C60 quantum confined layer of thickness 3nm and gold (Ψ=5.1eV) as metal contact. The capacitance and voltage characteristics at different temperatures from 100 K to 500 K and energy band gap are studied using Multi-dielectric Energy Band Diagram Program (MEBDP) simulation software, performed current-voltage transistor characteristics and analyzed the mobility of the charge carrier in the MQS sandwiched device structure using the Caughey-Thomas high saturation mobility model and the Lombardi surface mobility model. In these studies, we inferred a very low threshold voltage, when the donor concentration in the p-Si substrate is tuned between 1E16 to 1E17 cm-3 and a saturated flow of nanoamperes range of charge carrier at a low gate potential is even possible