43 research outputs found

    Development of Novel Sensor Devices for Total Ionization Dose Detection

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    abstract: Total dose sensing systems (or radiation detection systems) have many applications, ranging from survey monitors used to supervise the generated radioactive waste at nuclear power plants to personal dosimeters which measure the radiation dose accumulated in individuals. This dissertation work will present two different types of novel devices developed at Arizona State University for total dose sensing applications. The first detector technology is a mechanically flexible metal-chalcogenide glass (ChG) based system which is fabricated on low cost substrates and are intended as disposable total dose sensors. Compared to existing commercial technologies, these thin film radiation sensors are simpler in form and function, and cheaper to produce and operate. The sensors measure dose through resistance change and are suitable for applications such as reactor dosimetry, radiation chemistry, and clinical dosimetry. They are ideal for wearable devices due to the lightweight construction, inherent robustness to resist breaking when mechanically stressed, and ability to attach to non-flat objects. Moreover, their performance can be easily controlled by tuning design variables and changing incorporated materials. The second detector technology is a wireless dosimeter intended for remote total dose sensing. They are based on a capacitively loaded folded patch antenna resonating in the range of 3 GHz to 8 GHz for which the load capacitance varies as a function of total dose. The dosimeter does not need power to operate thus enabling its use and implementation in the field without requiring a battery for its read-out. As a result, the dosimeter is suitable for applications such as unattended detection systems destined for covert monitoring of merchandise crossing borders, where nuclear material tracking is a concern. The sensitive element can be any device exhibiting a known variation of capacitance with total ionizing dose. The sensitivity of the dosimeter is related to the capacitance variation of the radiation sensitive device as well as the high frequency system used for reading. Both technologies come with the advantage that they are easy to manufacture with reasonably low cost and sensing can be readily read-out.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

    High-Speed and Low-Energy On-Chip Communication Circuits.

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    Continuous technology scaling sharply reduces transistor delays, while fixed-length global wire delays have increased due to less wiring pitch with higher resistance and coupling capacitance. Due to this ever growing gap, long on-chip interconnects pose well-known latency, bandwidth, and energy challenges to high-performance VLSI systems. Repeaters effectively mitigate wire RC effects but do little to improve their energy costs. Moreover, the increased complexity and high level of integration requires higher wire densities, worsening crosstalk noise and power consumption of conventionally repeated interconnects. Such increasing concerns in global on-chip wires motivate circuits to improve wire performance and energy while reducing the number of repeaters. This work presents circuit techniques and investigation for high-performance and energy-efficient on-chip communication in the aspects of encoding, data compression, self-timed current injection, signal pre-emphasis, low-swing signaling, and technology mapping. The improved bus designs also consider the constraints of robust operation and performance/energy gains across process corners and design space. Measurement results from 5mm links on 65nm and 90nm prototype chips validate 2.5-3X improvement in energy-delay product.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/75800/1/jseo_1.pd

    Reconfigurable and multiband antennas with resonant and reactive loads

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    Reactive and resonant loads have been used from the very beginning of antenna design to improve impedance matching, bandwidth, and current distributions on antennas, and to create multiband and reconfigurable antennas.Trap loaded dipoles are one of the simplest resonator-loaded antennas and are traditionally loaded with either an inductor-capacitor pair or a quarter wavelength stub integrated into a dipole or monopole to create a second operating frequency at the trap resonant frequency. Adding resonant loads to antennas will only increase in popularity and practicality as filtennas are more often used for their SWaP improvements, better noise performance, and potential for additional degrees of reconfigurability. In this dissertation, I demonstrate that resonant loads can introduce lossy modes, and I significantly revise and expand the theory of the basic trap dipole antenna, which is a valuable aid in designing resonator loaded antennas with higher degrees of complexity. Based on the new analysis, I demonstrate novel series LC trap dipoles, dual-band inductor loaded trap dipoles, and parallel and series LC trap slots. The newly developed design process also allows for the integration of any kind of resonator or reactive load to be used to create trap style antennas. A reconfigurable load is also used to demonstrate novel tunable trap antennas. The design procedure is ultimately adaptable to any resonators that can be practically fabricated and physically incorporated into the antenna structure

    Design Techniques for On-Chip Global Signaling Over Lossy Transmission Lines.

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    This thesis describes techniques for global high-speed signaling over long (~10mm) lossy chip-serial transmission lines. With the increase in clock frequencies to multi-GHz rates, it has become impossible to move data across a die in a single clock cycle using conventional parallel bus-based communication. There are also reliability problems due to timing errors, skew, and jitter in fully synchronous systems. Noise, coupling, and inductive effects become significant for both intermediate length and global routing. A new on-chip lossy transmission line technique is developed and new driver and receiver circuitry for on-chip serial links are described. High-speed long-range serial signaling is best done over transmission lines. However, because of the relatively high sheet resistance of metal interconnect layers, on-chip transmission lines tend to be lossy. Matched termination with resistors and the proper selection of the characteristic impedance of the transmission line structure can effectively suppress ISI. Fast digital CMOS technology allows pulsed mode data drivers to operate at multi-GHz rates. A phase-tuned receiver samples and de-serializes the received signal. Since the sampling instant is tuned to match the received signal eye, there is no requirement to match the clock and signal routing or clock and signal delays. A complete self-testing on-chip transceiver communicating over a 5.8mm on-chip transmission line is implemented in 0.13um CMOS and tested. The measured BER at 9Gbps is less than 10^-10. Interleaving is usually necessary in high serial data rate serializer and de-serializer circuits. Multi-stage LC oscillators can be used to generate low phase noise multi-phases clocks required for interleaving. Conventional coupling between oscillators introduces out of phase currents, and this out of phase current causes a lower effective quality factor for each oscillator stage. However, capacitive coupling, a new technique, introduces in phase coupling between stages. Increased coupling with a ring of capacitors decreases phase spacing error dramatically and, in addition, the phase noise of multi-stages is also decreased thanks to in-phase coupling.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/58491/1/parkjy_1.pd

    An Energy-Efficient Reconfigurable Mobile Memory Interface for Computing Systems

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    The critical need for higher power efficiency and bandwidth transceiver design has significantly increased as mobile devices, such as smart phones, laptops, tablets, and ultra-portable personal digital assistants continue to be constructed using heterogeneous intellectual properties such as central processing units (CPUs), graphics processing units (GPUs), digital signal processors, dynamic random-access memories (DRAMs), sensors, and graphics/image processing units and to have enhanced graphic computing and video processing capabilities. However, the current mobile interface technologies which support CPU to memory communication (e.g. baseband-only signaling) have critical limitations, particularly super-linear energy consumption, limited bandwidth, and non-reconfigurable data access. As a consequence, there is a critical need to improve both energy efficiency and bandwidth for future mobile devices.;The primary goal of this study is to design an energy-efficient reconfigurable mobile memory interface for mobile computing systems in order to dramatically enhance the circuit and system bandwidth and power efficiency. The proposed energy efficient mobile memory interface which utilizes an advanced base-band (BB) signaling and a RF-band signaling is capable of simultaneous bi-directional communication and reconfigurable data access. It also increases power efficiency and bandwidth between mobile CPUs and memory subsystems on a single-ended shared transmission line. Moreover, due to multiple data communication on a single-ended shared transmission line, the number of transmission lines between mobile CPU and memories is considerably reduced, resulting in significant technological innovations, (e.g. more compact devices and low cost packaging to mobile communication interface) and establishing the principles and feasibility of technologies for future mobile system applications. The operation and performance of the proposed transceiver are analyzed and its circuit implementation is discussed in details. A chip prototype of the transceiver was implemented in a 65nm CMOS process technology. In the measurement, the transceiver exhibits higher aggregate data throughput and better energy efficiency compared to prior works

    Wireless power and data transmission to high-performance implantable medical devices

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    Novel techniques for high-performance wireless power transmission and data interfacing with implantable medical devices (IMDs) were proposed. Several system- and circuit-level techniques were developed towards the design of a novel wireless data and power transmission link for a multi-channel inductively-powered wireless implantable neural-recording and stimulation system. Such wireless data and power transmission techniques have promising prospects for use in IMDs such as biosensors and neural recording/stimulation devices, neural interfacing experiments in enriched environments, radio-frequency identification (RFID), smartcards, near-field communication (NFC), wireless sensors, and charging mobile devices and electric vehicles. The contributions in wireless power transfer are the development of an RFID-based closed-loop power transmission system, a high-performance 3-coil link with optimal design procedure, circuit-based theoretical foundation for magnetic-resonance-based power transmission using multiple coils, a figure-of-merit for designing high-performance inductive links, a low-power and adaptive power management and data transceiver ASIC to be used as a general-purpose power module for wireless electrophysiology experiments, and a Q-modulated inductive link for automatic load matching. In wireless data transfer, the contributions are the development of a new modulation technique called pulse-delay modulation for low-power and wideband near-field data communication and a pulse-width-modulation impulse-radio ultra-wideband transceiver for low-power and wideband far-field data transmission.Ph.D

    Sincronização em sistemas integrados a alta velocidade

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    Doutoramento em Engenharia ElectrotécnicaA distribui ção de um sinal relógio, com elevada precisão espacial (baixo skew) e temporal (baixo jitter ), em sistemas sí ncronos de alta velocidade tem-se revelado uma tarefa cada vez mais demorada e complexa devido ao escalonamento da tecnologia. Com a diminuição das dimensões dos dispositivos e a integração crescente de mais funcionalidades nos Circuitos Integrados (CIs), a precisão associada as transições do sinal de relógio tem sido cada vez mais afectada por varia ções de processo, tensão e temperatura. Esta tese aborda o problema da incerteza de rel ogio em CIs de alta velocidade, com o objetivo de determinar os limites do paradigma de desenho sí ncrono. Na prossecu ção deste objectivo principal, esta tese propõe quatro novos modelos de incerteza com âmbitos de aplicação diferentes. O primeiro modelo permite estimar a incerteza introduzida por um inversor est atico CMOS, com base em parâmetros simples e su cientemente gen éricos para que possa ser usado na previsão das limitações temporais de circuitos mais complexos, mesmo na fase inicial do projeto. O segundo modelo, permite estimar a incerteza em repetidores com liga ções RC e assim otimizar o dimensionamento da rede de distribui ção de relógio, com baixo esfor ço computacional. O terceiro modelo permite estimar a acumula ção de incerteza em cascatas de repetidores. Uma vez que este modelo tem em considera ção a correla ção entre fontes de ruí do, e especialmente util para promover t ecnicas de distribui ção de rel ogio e de alimentação que possam minimizar a acumulação de incerteza. O quarto modelo permite estimar a incerteza temporal em sistemas com m ultiplos dom ínios de sincronismo. Este modelo pode ser facilmente incorporado numa ferramenta autom atica para determinar a melhor topologia para uma determinada aplicação ou para avaliar a tolerância do sistema ao ru ído de alimentação. Finalmente, usando os modelos propostos, são discutidas as tendências da precisão de rel ogio. Conclui-se que os limites da precisão do rel ogio são, em ultima an alise, impostos por fontes de varia ção dinâmica que se preveem crescentes na actual l ogica de escalonamento dos dispositivos. Assim sendo, esta tese defende a procura de solu ções em outros ní veis de abstração, que não apenas o ní vel f sico, que possam contribuir para o aumento de desempenho dos CIs e que tenham um menor impacto nos pressupostos do paradigma de desenho sí ncrono.Distributing a the clock simultaneously everywhere (low skew) and periodically everywhere (low jitter) in high-performance Integrated Circuits (ICs) has become an increasingly di cult and time-consuming task, due to technology scaling. As transistor dimensions shrink and more functionality is packed into an IC, clock precision becomes increasingly a ected by Process, Voltage and Temperature (PVT) variations. This thesis addresses the problem of clock uncertainty in high-performance ICs, in order to determine the limits of the synchronous design paradigm. In pursuit of this main goal, this thesis proposes four new uncertainty models, with di erent underlying principles and scopes. The rst model targets uncertainty in static CMOS inverters. The main advantage of this model is that it depends only on parameters that can easily be obtained. Thus, it can provide information on upcoming constraints very early in the design stage. The second model addresses uncertainty in repeaters with RC interconnects, allowing the designer to optimise the repeater's size and spacing, for a given uncertainty budget, with low computational e ort. The third model, can be used to predict jitter accumulation in cascaded repeaters, like clock trees or delay lines. Because it takes into consideration correlations among variability sources, it can also be useful to promote oorplan-based power and clock distribution design in order to minimise jitter accumulation. A fourth model is proposed to analyse uncertainty in systems with multiple synchronous domains. It can be easily incorporated in an automatic tool to determine the best topology for a given application or to evaluate the system's tolerance to power-supply noise. Finally, using the proposed models, this thesis discusses clock precision trends. Results show that limits in clock precision are ultimately imposed by dynamic uncertainty, which is expected to continue increasing with technology scaling. Therefore, it advocates the search for solutions at other abstraction levels, and not only at the physical level, that may increase system performance with a smaller impact on the assumptions behind the synchronous design paradigm

    RAD - Research and Education 2010

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    Cryogenic Control Beyond 100 Qubits

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    Quantum computation has been a major focus of research in the past two decades, with recent experiments demonstrating basic algorithms on small numbers of qubits. A large-scale universal quantum computer would have a profound impact on science and technology, providing a solution to several problems intractable for classical computers. To realise such a machine, today's small experiments must be scaled up, and a system must be built which provides control and measurement of many hundreds of qubits. A device of this scale is challenging: qubits are highly sensitive to their environment, and sophisticated isolation techniques are required to preserve the qubits' fragile states. Solid-state qubits require deep-cryogenic cooling to suppress thermal excitations. Yet current state-of-the-art experiments use room-temperature electronics which are electrically connected to the qubits. This thesis investigates various scalable technologies and techniques which can be used to control quantum systems. With the requirements for semiconductor spin-qubits in mind, several custom electronic systems, to provide quantum control from deep cryogenic temperatures, are designed and measured. A system architecture is proposed for quantum control, providing a scalable approach to executing quantum algorithms on a large number of qubits. Control of a gallium arsenide qubit is demonstrated using a cryogenically operated FPGA driving custom gallium arsenide switches. The cryogenic performance of a commercial FPGA is measured, as the main logic processor in a cryogenic quantum control system, and digital-to-analog converters are analysed during cryogenic operation. Recent work towards a 100-qubit cryogenic control system is shown, including the design of interconnect solutions and multiplexing circuitry. With qubit fidelity over the fault-tolerant threshold for certain error correcting codes, accompanying control platforms will play a key role in the development of a scalable quantum machine
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