Switched Capacitor Loop Filter 와 Source Switched Charge Pump 를 이용한 Phase-Locked Loop 의 설계

학위논문(석사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022.2. 정덕균.This thesis proposes a low integrated RMS jitter and low reference spur phase locked loop (PLL) using a switched capacitor loop filter and source switched charge pump. The PLL employs a single tunable charge pump which reduces current mis match across wide control voltage range and charge sharing effect to get high perfor mance of reference spur level. The switched capacitor loop filter is adopted to achieve insensitivity to temperature, supply voltage, and process variation of a resistor. The proposed PLL covers a wide frequency range and has a low integrated RMS jitter and low reference spur level to target various interface standards. The mechanism of switched capacitor loop filter and source switched charge pump is analyzed. Fabricated in 40 nm CMOS technology, the proposed analog PLL provides four phase for a quarter-rate transmitter, consumes 6.35 mW at 12 GHz using 750 MHz reference clock, and occupies an 0.008 mm2 with an integrated RMS jitter (10 kHz to 100 MHz) of 244.8 fs. As a result, the PLL achieves a figure of merit (FoM) of -244.2 dB with high power efficiency of 0.53 mW/GHz, and reference spur level is -60.3 dBc.본 논문에서는 낮은 RMS jitter 와 낮은 레퍼런스 스퍼를 가지며 스위치축전기 루프 필터와 소스 스위치 전하 펌프를 이용한 PLL 을 제안한다. 제안된 PLL 은 레퍼런스 스퍼의 성능을 위해 넓은 컨트롤 전압의 범위 동안 전류의 오차를 줄여주고 전하 공유 효과를 줄여주는 하나의 조절 가능한 전하 펌프를 사용하였다. 저항의 온도, 공급 전압, 공정 변화에 따른 민감도를 낮추기 위해 스위치 축전기 루프 필터가 사용되었다. 다양한 인터페이스 표준을 지원하기 위해 제안하는 PLL 은 넓은 주파수 범위를 지원하고 낮은 RMS jitter 와 낮은 레퍼런스 스퍼를 갖는다. 스위치 축전기 루프 필터와 소스 스위치 전하 펌프의 동작 원리에 대해 분석하였다. 40 nm CMOS 공정으로 제작되었으며, 제안된 회로는 quarter-rate 송신기를 위해 4 개의 phase 를 만들어내며 750 MHz 의 레퍼런스 클락을 이용하여 12 GHz 에서 6.35 mW 의 power 를 소모하고 0.008mm2 의 유효 면적을 차지하고 10 kHz 부터 100 MHz 까지 적분했을 때의 RMS jitter 값은 244.8fs 이다. 제안하는 PLL 은 -244.2 dB 의 FoM, 0.53 mW/GHz 의 power 효율을 달성했으며 레퍼런스 스퍼는 -60.3 dBc 이다CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 3 CHAPTER 2 BACKGROUNDS 4 2.1 CLOCK GENERATION IN SERIAL LINK 4 2.2 PLL BUILDING BLOCKS 6 2.2.1 OVERVIEW 6 2.2.2 PHASE FREQUENCY DETECTOR 7 2.2.3 CHARGE PUMP AND LOOP FILTER 9 2.2.4 VOLTAGE CONTROLLED OSCILLATOR 10 2.2.5 FREQUENCY DIVIDER 13 2.3 PLL LOOP ANALYSIS 15 CHAPTER 3 PLL WITH SWITCHED CAPACITOR LOOP FILTER AND SOURCE SWITCHED CHARGE PUMP 19 3.1 DESIGN CONSIDERATION 19 3.2 PROPOSED ARCHITECTURE 21 3.3 CIRCUIT IMPLEMENTATION 23 3.3.1 PHASE FREQUENCY DETECTOR 23 3.3.2 SOURCE SWITCHED CHARGE PUMP 26 3.3.3 SWITCHED CAPACITOR LOOP FILTER 30 3.3.4 VOLTAGE CONTROLLED OSCILLATOR 35 3.3.5 POST VCO AMPLIFIER 39 3.3.6 FREQUENCY DIVIDER 40 CHAPTER 4 MEASUREMENT RESULTS 43 4.1 CHIP PHOTOMICROGRAPH 43 4.2 MEASUREMENT SETUP 45 4.3 MEASURED PHASE NOISE AND REFERENCE SPUR 47 4.4 PERFORMANCE SUMMARY 50 CHAPTER 5 CONCLUSION 52 BIBLIOGRAPHY 53 초 록 58석

Digital enhancement techniques for fractional-N frequency synthesizers

Meeting the demand for unprecedented connectivity in the era of internet-of-things (IoT) requires extremely energy efficient operation of IoT nodes to extend battery life. Managing the data traffic generated by trillions of such nodes also puts severe energy constraints on the data centers. Clock generators that are essential elements in these systems consume significant power and therefore must be optimized for low power and high performance. The focus of this thesis is on improving the energy efficiency of frequency synthesizers and clocking modules by exploring design techniques at both the architectural and circuit levels. In the first part of this work, a digital fractional-N phase locked loop (FNPLL) that employs a high resolution time-to-digital converter (TDC) and a truly ΔΣ fractional divider to achieve low in-band noise with a wide bandwidth is presented. The fractional divider employs a digital-to-time converter (DTC) to cancel out ΔΣ quantization noise in time domain, thus alleviating TDC dynamic range requirements. The proposed digital architecture adopts a narrow range low-power time-amplifier based TDC (TA-TDC) to achieve sub 1ps resolution. Fabricated in 65nm CMOS process, the prototype PLL achieves better than -106dBc/Hz in-band noise and 3MHz PLL bandwidth at 4.5GHz output frequency using 50MHz reference. The PLL achieves excellent jitter performance of 490fsrms, while consumes only 3.7mW. This translates to the best reported jitter-power figure-of-merit (FoM) of -240.5dB among previously reported FNPLLs. Phase noise performance of ring oscillator based digital FNPLLs is severely compromised by conflicting bandwidth requirements to simultaneously suppress oscillator phase and quantization noise introduced by the TDC, ΔΣ fractional divider, and digital-to-analog converter (DAC). As a consequence, their FoM that quantifies the power-jitter tradeoff is at least 25dB worse than their LC-oscillator based FNPLL counterparts. In the second part of this thesis, we seek to close this performance gap by extending PLL bandwidth using quantization noise cancellation techniques and by employing a dual-path digital loop filter to suppress the detrimental impact of DAC quantization noise. A prototype was implemented in a 65nm CMOS process operating over a wide frequency range of 2.0GHz-5.5GHz using a modified extended range multi-modulus divider with seamless switching. The proposed digital FNPLL achieves 1.9psrms integrated jitter while consuming only 4mW at 5GHz output. The measured in-band phase noise is better than -96 dBc/Hz at 1MHz offset. The proposed FNPLL achieves wide bandwidth up to 6MHz using a 50 MHz reference and its FoM is -228.5dB, which is at about 20dB better than previously reported ring-based digital FNPLLs. In the third part, we propose a new multi-output clock generator architecture using open loop fractional dividers for system-on-chip (SoC) platforms. Modern multi-core processors use per core clocking, where each core runs at its own speed. The core frequency can be changed dynamically to optimize for performance or power dissipation using a dynamic frequency scaling (DFS) technique. Fast frequency switching is highly desirable as long as it does not interrupt code execution; therefore it requires smooth frequency transitions with no undershoots. The second main requirement in processor clocking is the capability of spread spectrum frequency modulation. By spreading the clock energy across a wide bandwidth, the electromagnetic interference (EMI) is dramatically reduced. A conventional PLL clock generation approach suffers from a slow frequency settling and limited spread spectrum modulation capabilities. The proposed open loop fractional divider architecture overcomes the bandwidth limitation in fractional-N PLLs. The fractional divider switches the output frequency instantaneously and provides an excellent spread spectrum performance, where precise and programmable modulation depth and frequency can be applied to satisfy different EMI requirements. The fractional divider has unlimited modulation bandwidth resulting in spread spectrum modulation with no filtering, unlike fractional-N PLL; consequently it achieves higher EMI reduction. A prototype fractional divider was implemented in a 65nm CMOS process, where the measured peak-to-peak jitter is less than 27ps over a wide frequency range from 20MHz to 1GHz. The total power consumption is about 3.2mW for 1GHz output frequency. The all-digital implementation of the divider occupies the smallest area of 0.017mm2 compared to state-of-the-art designs. As the data rate of serial links goes higher, the jitter requirements of the clock generator become more stringent. Improving the jitter performance of conventional PLLs to less than (200fsrms) always comes with a large power penalty (tens of mWs). This is due to the PLL coupled noise bandwidth trade-off, which imposes stringent noise requirements on the oscillator and/or loop components. Alternatively, an injection-locked clock multiplier (ILCM) provides many advantages in terms of phase noise, power, and area compared to classical PLLs, but they suffer from a narrow lock-in range and a high sensitivity to PVT variations especially at a large multiplication factor (N). In the fourth part of this thesis, a low-jitter, low-power LC-based ILCM with a digital frequency-tracking loop (FTL) is presented. The proposed FTL relies on a new pulse gating technique to continuously tune the oscillator's free-running frequency. The FTL ensures robust operation across PVT variations and resolves the race condition existing in injection locked PLLs by decoupling frequency tuning from the injection path. As a result, the phase locking condition is only determined by the injection path. This work also introduces an accurate theoretical large-signal analysis for phase domain response (PDR) of injection locked oscillators (ILOs). The proposed PDR analysis captures the asymmetric nature of ILO's lock-in range, and the impact of frequency error on injection strength and phase noise performance. The proposed architecture and analysis are demonstrated by a prototype fabricated in 65 nm CMOS process with active area of 0.25mm2. The prototype ILCM multiplies the reference frequency by 64 to generate an output clock in the range of 6.75GHz-8.25GHz. A superior jitter performance of 190fsrms is achieved, while consuming only 2.25mW power. This translates to a best FoM of -251dB. Unlike conventional PLLs, ILCMs have been fundamentally limited to only integer-N operation and cannot synthesize fractional-N frequencies. In the last part of this thesis, we extend the merits of ILCMs to fractional-N and overcome this fundamental limitation. We employ DTC-based QNC techniques in order to align injected pulses to the oscillator's zero crossings, which enables it to pull the oscillator toward phase lock, thus realizing a fractional-N ILCM. Fabricated in 65nm CMOS process, a prototype 20-bit fractional-N ILCM with an output range of 6.75GHz-8.25GHz consumes only 3.25mW. It achieves excellent jitter performance of 110fsrms and 175fsrms in integer- and fractional-N modes respectively, which translates to the best-reported FoM in both integer- (-255dB) and fractional-N (-252dB) modes. The proposed fractional-N ILCM also features the first-reported rapid on/off capability, where the transient absolute jitter performance at wake-up is bounded below 4ps after less than 4ns. This demonstrates almost instantaneous phase settling. This unique capability enables tremendous energy saving by turning on the clock multiplier only when needed. This energy proportional operation leverages idle times to save power at the system-level of wireline and wireless transceivers

캘리브레이션이 필요없는 위상고정 루프의 설계

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2017. 2. 김재하.A PVT-insensitive-bandwidth PLL and a chirp frequency synthesizer PLL are proposed using a constant-relative-gain digitally-controlled oscillator (DCO), a constant-gain time-to-digital converter (TDC), and a simple digital loop filter (DLF) without an explicit calibration or additional circuit components. A digital LC-PLL that realizes a PVT-insensitive loop bandwidth (BW) by using the constant-relative-gain LC-DCO and constant-gain TDC is proposed. In other words, based on ratiometric circuit designs, the LC-DCO can make a fixed percent change to its frequency for a unit change in its digital input and the TDC can maintain a fixed range and resolution measured in reference unit intervals (UIs) across PVT variations. With such LC-DCO and TDC, the proposed PLL can realize a bandwidth which is a constant fraction of the reference frequency even with a simple proportional-integral digital loop filter without any explicit calibration loops. The prototype digital LC-PLL fabricated in a 28-nm CMOS demonstrates a frequency range of 8.38~9.34 GHz and 652-fs,rms integrated jitter from 10-kHz to 1-GHz at 8.84-GHz while dissipating 15.2-mW and occupying 0.24-mm^2. Also, the PLL across three different die samples and supply voltage ranging from 1.0 to 1.2V demonstrates a nearly constant BW at 822-kHz with the variation of ±4.25-% only. A chirp frequency synthesizer PLL (FS-PLL) that is capable of precise triangular frequency modulation using type-III digital LC-PLL architecture for X-band FMCW imaging radar is proposed. By employing a phase-modulating two-point modulation (TPM), constant-gain TDC, and a simple second-order DLF with polarity-alternating frequency ramp estimator, the PLL achieves a gain self-tracking TPM realizing a frequency chirp with fast chirp slope (=chirp BW/chirp period) without increasing frequency errors around the turn-around points, degrading the effective resolution achievable. A prototype chirp FS-PLL fabricated in a 65nm CMOS demonstrates that the PLL can generate a precise triangular chirp profile centered at 8.9-GHz with 940-MHz bandwidth and 28.8-us period with only 1.9-MHz,rms frequency error including the turn-around points and 14.8-mW power dissipation. The achieved 32.63-MHz/us chirp slope is higher than that of FMCW FS-PLLs previously reported by 2.6x.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 5 CHAPTER 2 CONVENTIONAL PHASE-LOCKED LOOP 7 2.1 CHARGE-PUMP PLL 7 2.1.1 OPERATING PRINCIPLE 7 2.1.2 LOOP DYNAMICS 9 2.2 DIGITAL PLL 10 2.2.1 OPERATING PRINCIPLE 11 2.2.2 LOOP DYNAMICS 12 CHAPTER 3 VARIATIONS ON PHASE-LOCKED LOOP 14 3.1 OSCILLATOR GAIN VARIATION 14 3.1.1 RING VOLTAGE-CONTROLLED OSCILLATOR 15 3.1.2 LC VOLTAGE-CONTROLLED OSCILLATOR 17 3.1.3 LC DIGITALLY-CONTROLLED OSCILLATOR 19 3.2 PHASE DETECTOR GAIN VARIATION 20 3.2.1 LINEAR PHASE DETECTOR 20 3.2.2 LINEAR TIME-TO-DIGITAL CONVERTER 21 CHAPTER 4 PROPOSED DCO AND TDC FOR CALIBRATION-FREE PLL 23 4.1 DIGTALLY-CONTROLLED OSCILLATOR (DCO) 25 4.1.1 OVERVIEW 24 4.1.2 CONSTANT-RELATIVE-GAIN DCO 26 4.2 TIME-TO-DIGITAL CONVERTER (TDC) 28 4.2.1 OVERVIEW 28 4.2.2 CONSTANT-GAIN TDC 30 CHAPTER 5 PVT-INSENSITIVE-BANDWIDTH PLL 35 5.1 OVERVIEW 36 5.2 PRIOR WORKS 37 5.3 PROPOSED PVT-INSENSITIVE-BANDWIDTH PLL 39 5.4 CIRCUIT IMPLEMENTATION 41 5.4.1 CAPACITOR-TUNED LC-DCO 41 5.4.2 TRANSFORMER-TUNED LC-DCO 45 5.4.3 OVERSAMPLING-BASED CONSTANT-GAIN TDC 49 5.4.4 PHASE DIGITAL-TO-ANALOG CONVERTER 52 5.4.5 DIGITAL LOOP FILTER 54 5.4.6 FREQUENCY DIVIDER 55 5.4.7 BANG-BANG PHASE-FREQUENCY DETECTOR 56 5.5 CELL-BASED DESIGN FLOW 57 5.6 MEASUREMENT RESULTS 58 CHAPTER 6 CHIRP FREQUENCY SYNTHESIZER PLL 66 6.1 OVERVIEW 67 6.2 PRIOR WORKS 71 6.3 PROPOSED CHIRP FREQUENCY SYNTHESIZER PLL 75 6.4 CIRCUIT IMPLEMENTATION 83 6.4.1 SECOND-ORDER DIGITAL LOOP FILTER 83 6.4.2 PHASE MODULATOR 84 6.4.3 CONSTANT-GAIN TDC 85 6.4.4 VRACTOR-BASED LC-DCO 87 6.4.5 OVERALL CLOCK CHAIN 90 6.5 MEASUREMENT RESULTS 91 6.6 SIGNAL-TO-NOISE RATIO OF RADAR 98 CHAPTER 7 CONCLUSION 100 BIBLIOGRAPHY 102 초록 109Docto

Ring oscillator based injection locked clock multiplier

This thesis describes a ring-based injection locked clock multiplier (ILCM) designed with the goal of generating a high-frequency and low-jitter clock. Building on prior research done on injection locking, this design uses a reference frequency doubling technique to push the noise bandwidth of the circuit to Fref/3 to suppress DCO noise to a large extent. A background duty cycle error correction technique is employed to correct errors on the doubled clock that could be detrimental to performance. The design also modifies an existing architecture to achieve type-II suppression of DCO noise in order to fully suppress the flicker noise which becomes prevalent in low process nodes. The prototype ILCM was fabricated in TSMC 65 nm CMOS technology. Thorough testing was performed to characterize the effectiveness of the aforementioned techniques. The circuit achieves 340 fsrms integrated jitter when operating at 5 GHz while only consuming 5.3 mW of power. The ILCM's figure of merit, -242.4 dB, is on par with state-of-the-art ring-based clock multipliers while operating at a much higher output frequency and multiplication factor than previously published work. These results indicate the effectiveness of reference frequency doubling in a ring-based, high-performance clock multiplier design