A Communication Monitor for Wireless Sensor Networks Based on Software Defined Radio

Link quality estimation of reliability-crucial wireless sensor networks (WSNs) is often limited by the observability and testability of single-chip radio transceivers. The estimation is often based on collection of packer-level statistics, including packet reception rate, or vendor-specific registers, such as CC2420's Received Signal Strength Indicator (RSSI) and Link Quality Indicator (LQI). The speed or accuracy of such metrics limits the performance of reliability mechanisms built in wireless sensor networks. To improve link quality estimation in WSNs, we designed a powerful wireless communication monitor based on Software Defined Radio (SDR). We studied the relations between three implemented link quality metrics and packet reception rate under different channel conditions. Based on a comparison of the metrics' relative advantages, we proposed using a combination of them for fast and accurate estimation of a sensor network link

Wi-PoS : a low-cost, open source ultra-wideband (UWB) hardware platform with long range sub-GHz backbone

Ultra-wideband (UWB) localization is one of the most promising approaches for indoor localization due to its accurate positioning capabilities, immunity against multipath fading, and excellent resilience against narrowband interference. However, UWB researchers are currently limited by the small amount of feasible open source hardware that is publicly available. We developed a new open source hardware platform, Wi-PoS, for precise UWB localization based on Decawave’s DW1000 UWB transceiver with several unique features: support of both long-range sub-GHz and 2.4 GHz back-end communication between nodes, flexible interfacing with external UWB antennas, and an easy implementation of the MAC layer with the Time-Annotated Instruction Set Computer (TAISC) framework. Both hardware and software are open source and all parameters of the UWB ranging can be adjusted, calibrated, and analyzed. This paper explains the main specifications of the hardware platform, illustrates design decisions, and evaluates the performance of the board in terms of range, accuracy, and energy consumption. The accuracy of the ranging system was below 10 cm in an indoor lab environment at distances up to 5 m, and accuracy smaller than 5 cm was obtained at 50 and 75 m in an outdoor environment. A theoretical model was derived for predicting the path loss and the influence of the most important ground reflection. At the same time, the average energy consumption of the hardware was very low with only 81 mA for a tag node and 63 mA for the active anchor nodes, permitting the system to run for several days on a mobile battery pack and allowing easy and fast deployment on sites without an accessible power supply or backbone network. The UWB hardware platform demonstrated flexibility, easy installation, and low power consumption

A Comprehensive Workflow for General-Purpose Neural Modeling with Highly Configurable Neuromorphic Hardware Systems

In this paper we present a methodological framework that meets novel requirements emerging from upcoming types of accelerated and highly configurable neuromorphic hardware systems. We describe in detail a device with 45 million programmable and dynamic synapses that is currently under development, and we sketch the conceptual challenges that arise from taking this platform into operation. More specifically, we aim at the establishment of this neuromorphic system as a flexible and neuroscientifically valuable modeling tool that can be used by non-hardware-experts. We consider various functional aspects to be crucial for this purpose, and we introduce a consistent workflow with detailed descriptions of all involved modules that implement the suggested steps: The integration of the hardware interface into the simulator-independent model description language PyNN; a fully automated translation between the PyNN domain and appropriate hardware configurations; an executable specification of the future neuromorphic system that can be seamlessly integrated into this biology-to-hardware mapping process as a test bench for all software layers and possible hardware design modifications; an evaluation scheme that deploys models from a dedicated benchmark library, compares the results generated by virtual or prototype hardware devices with reference software simulations and analyzes the differences. The integration of these components into one hardware-software workflow provides an ecosystem for ongoing preparative studies that support the hardware design process and represents the basis for the maturity of the model-to-hardware mapping software. The functionality and flexibility of the latter is proven with a variety of experimental results

NaNet: a Low-Latency, Real-Time, Multi-Standard Network Interface Card with GPUDirect Features

While the GPGPU paradigm is widely recognized as an effective approach to high performance computing, its adoption in low-latency, real-time systems is still in its early stages. Although GPUs typically show deterministic behaviour in terms of latency in executing computational kernels as soon as data is available in their internal memories, assessment of real-time features of a standard GPGPU system needs careful characterization of all subsystems along data stream path. The networking subsystem results in being the most critical one in terms of absolute value and fluctuations of its response latency. Our envisioned solution to this issue is NaNet, a FPGA-based PCIe Network Interface Card (NIC) design featuring a configurable and extensible set of network channels with direct access through GPUDirect to NVIDIA Fermi/Kepler GPU memories. NaNet design currently supports both standard - GbE (1000BASE-T) and 10GbE (10Base-R) - and custom - 34~Gbps APElink and 2.5~Gbps deterministic latency KM3link - channels, but its modularity allows for a straightforward inclusion of other link technologies. To avoid host OS intervention on data stream and remove a possible source of jitter, the design includes a network/transport layer offload module with cycle-accurate, upper-bound latency, supporting UDP, KM3link Time Division Multiplexing and APElink protocols. After NaNet architecture description and its latency/bandwidth characterization for all supported links, two real world use cases will be presented: the GPU-based low level trigger for the RICH detector in the NA62 experiment at CERN and the on-/off-shore data link for KM3 underwater neutrino telescope