VHDL Design and Analysis of Decoder of Parallel Turbo Product Code

Recently, the trend of wireless communication is changed from the conventional narrow-band voice service to the wide-band multimedia service. In 1993, Berrou et al introduced a new class of error correcting codes for digital transmission : the "turbo code". Therefore, the important problems of high-speed applications of turbo decoder are decoding delay and computational complexity. Therefore, the real difficulty in the field of channel coding is essentially a problem of decoding complexity of powerful codes. Another interest area of channel coding scheme is LDPC(Low Density Parity Check) code. But the encoder structure is very complicate. Therefore, it highly required channel coding scheme with simple encoder/decoder structure and good error performance in order to apply for wireless multimedia communications such as Ka-band satellite and wide-band mobile communication systems. Recently, there has been intensive focus on TPC(Turbo Product Code) which has low latency and simple structures compare with turbo code and LDPC. It achieve near-optimum performance at low signal-to-noise ratio. TPCs are two dimensional code constructed from small component codes. Different than original TPC decoder, which performs row and column decoding in a serial fashion, a parallel decoder structure to reduce the latency is proposed in this thesis. Proposed TPC decoder needs only one delay element in contrast to conventional algorithm, which needs two delay elements. This thesis analyzes the parallel TPC decoder by mathematical theory and compares the performance between parallel algorithm and conventional algorithm by computer simulation. Also this thesis establishes parameters by fixed-point simulation for VHDL implementation. From results of computer simulation and VHDL implementation, this thesis shows that decoding time of parallel algorithm is halved with this structure while maintaining the same performance level.제 1 장 서 론 1 제 2 장 Turbo Product Code의 구조분석 3 2.1 반복 복호와 외부정보 3 2.2 Turbo Product Code의 부호화기 구성 10 2.3 Turbo Product Code의 복호기 구성 12 제 3 장 병렬 Turbo Product Code 구조 23 3.1 부분 병렬 Turbo Product Code분석 및 구조 23 3.2 병렬 Turbo Product Code분석 및 구조 25 3.3 모의 실험 결과 27 제 4 장 최적 파라미터 설계 30 4.1 수신신호의 양자화 범위에 따른 성능 30 4.2 수신신호의 양자화 비트수에 따른 성능 31 제 5 장 병렬 Turbo Product Code VHDL 설계 32 제 6장 결론 40 참고문헌 4

Comparison of Polar Decoders with Existing Low-Density Parity-Check and Turbo Decoders

Polar codes are a recently proposed family of provably capacity-achieving error-correction codes that received a lot of attention. While their theoretical properties render them interesting, their practicality compared to other types of codes has not been thoroughly studied. Towards this end, in this paper, we perform a comparison of polar decoders against LDPC and Turbo decoders that are used in existing communications standards. More specifically, we compare both the error-correction performance and the hardware efficiency of the corresponding hardware implementations. This comparison enables us to identify applications where polar codes are superior to existing error-correction coding solutions as well as to determine the most promising research direction in terms of the hardware implementation of polar decoders.Comment: Fixes small mistakes from the paper to appear in the proceedings of IEEE WCNC 2017. Results were presented in the "Polar Coding in Wireless Communications: Theory and Implementation" Worksho

A Study on Low Computational Complexity and High-Speed Algorithm of Iterative Codes and FPGA Implementation

Concatenate coding schemes are considered as being the best solution for powerful protection of digital information against nonlinear and fading noise channel. However, the performance of concatenate coding scheme is away from Shannon's limit. In 1993, Berrou and al introduced a new class of error correcting codes for digital transmission : the "turbo code". Turbo codes have been shown to perform near the capacity limit on the additive white Gaussian noise (AWGN) channels. As a powerful coding technique, turbo code offers great promise for improving the reliability of communication over wireless channels. Another interest area of channel coding scheme is LDPC(Low Density Parity Check) code. The high definition television(HDTV) satellite standard , known as the Digital Video Broadcasting (DVB-S2) transmission system employs a LDPC coding technique as a channel coding scheme. Unlike turbo codes, LDPC codes have easily parallelizable decoding algorithm which consists of simple operation such as addition, comparison and look-up table. Moreover the degree of parallelism is “adjustable” which makes it easy to trade-off throughput and complexity. However DVB-S2 system requires large block size and large number of iterations to near Shannon’s limit. The standard recommends that LDPC coded block size has 64800, and number of iteration is about 70 in the case of half coding rate. A large number of iterations for a large block size give rise to a large number of computation operations, mass power consumption, and decoding delay. It is necessary to reduce the iteration numbers and computation operations without performance degradation in order to implement with low power consumption. This thesis proposes the two kinds of simplified complexity reduced algorithm. First, sequential decoding with partial group is proposed. It has same H/W complexity, and fewer number of iteration’s are required at same performance in comparison with conventional decoder algorithm. Secondly, early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. In this way, because early detected edges are not computed from following iterations, the computational complexity of further processing is reduced. However the encoder structure is very complicate. Therefore, it highly required channel coding scheme with simple encoder/decoder structure and good error performance in order to apply for wireless multimedia communications such as Ka-band satellite and wide-band mobile communication systems. Recently, there has been intensive focus on turbo product code(TPC) which has low latency and simple structures compare with turbo code. It achieve near-optimum performance at low signal-to-noise ratio. TPCs are two dimensional code constructed from small component codes. Different than original TPC decoder, which performs row and column decoding in a serial fashion, this thesis proposes a parallel decoder structure to reduce the latency. Furthermore, only one delay element is needed in contrast to two delay elements, i.e., decoding time is halved with this structure while maintaining the same performance level. Therefore, this thesis proposes the parallel TPC decoder and analyzes its performance. From the thesis, we describe the low latency and/or computational algorithm of three iterative codes.Abstract ii Nomenclature iv 제 1 장 서 론 1 제 2 장 블록 부호를 이용한 반복 부호 3 2.1 Low Density Parity Check codes 3 2.1.1 LPDC 복호 알고리즘 5 2.1.2 Low Computation Complexity 알고리즘 9 2.2 Turbo Product Codes 22 2.2.1 고속 복호 알고리즘 23 2.2.2 VHDL 모델링 28 제 3 장 트렐리스 기반의 반복 부호 31 3.1 Turbo Codes 31 3.1.1 Turbo 부호의 알고리즘 분석 32 3.1.2 Turbo 부호의 복호기 구현 34 3.2 고속화 방안 37 제 4 장 결 론 40 참고문헌 4

On chip interconnects for multiprocessor turbo decoding architectures

International audienc

NanoMagnetic Logic Microprocessor Hierarchical Power Model

The interest on emerging nanotechnologies has been recently focused on NanoMagnetic Logic (NML), which has unique appealing features. NML circuits have a very low power consumption and, due to their magnetic nature, they maintain the information safely stored even without power supply. The nature of these circuits is highly different from the CMOS ones. As a consequence, to better understand NML logic, complex circuits and not only simple gates must be designed. This constraint calls for a new design and simulation methodology. It should efficiently encompass manifold properties: 1) being based on commonly used hardware description language (HDL) in order to easily manage complexity and hierarchy; 2) maintaining a clear link with physical characteristics 3) modeling performance aspects like speed and power, together with logic behavior. In this contribution we present a VHDL behavioral model for NML circuits, which allows to evaluate not only logic behavior but also power dissipation. It is based on a technological solution called ``snake-clock''. We demonstrate this model on a case study which offers the right variety of internal substructures to test the method: a four bit microprocessor designed using asynchronous logic. The model enables a hierarchical bottom-up evaluation of the processor logic behavior, area and power dissipation, which we evaluated using as benchmark a division algorithm. Results highlight the flexibility and the efficiency of this model, and the remarkable improvements that it brings to the analysis of NML circuit