Matrix multiplication using quantum-dot cellular automata to implement conventional microelectronics

Quantum-dot cellular automata (QCA) shows promise as a post silicon CMOS, low power computational technology. Nevertheless, to generalize QCA for next-generation digital devices, the ability to implement conventional programmable circuits based on NOR, AND, and OR gates is necessary. To this end, we devise a new QCA structure, the QCA matrix multiplier (MM), employing the standard Coulomb blocked, five quantum dot (QD) QCA cell and quasi-adiabatic switching for sequential data latching in the QCA cells. Our structure can multiply two N x M matrices, using one input and one bidirectional input/output data line. The calculation is highly parallelizable, and it is possible to achieve reduced calculation time in exchange for increasing numbers of parallel matrix multiplier units. We show convergent, ab initio simulation results using the Intercellular Hartree Approximation for one, three, and nine matrix multiplier units. The structure can generally implement any programmable logic array (PLA) or any matrix multiplication based operation.Comment: 14 pages, 9 figures, supplemental informatio

Fault and Defect Tolerant Computer Architectures: Reliable Computing With Unreliable Devices

This research addresses design of a reliable computer from unreliable device technologies. A system architecture is developed for a fault and defect tolerant (FDT) computer. Trade-offs between different techniques are studied and yield and hardware cost models are developed. Fault and defect tolerant designs are created for the processor and the cache memory. Simulation results for the content-addressable memory (CAM)-based cache show 90% yield with device failure probabilities of 3 x 10(-6), three orders of magnitude better than non fault tolerant caches of the same size. The entire processor achieves 70% yield with device failure probabilities exceeding 10(-6). The required hardware redundancy is approximately 15 times that of a non-fault tolerant design. While larger than current FT designs, this architecture allows the use of devices much more likely to fail than silicon CMOS. As part of model development, an improved model is derived for NAND Multiplexing. The model is the first accurate model for small and medium amounts of redundancy. Previous models are extended to account for dependence between the inputs and produce more accurate results

Crosstalk computing: circuit techniques, implementation and potential applications

Title from PDF of title [age viewed January 32, 2022Dissertation advisor: Mostafizur RahmanVitaIncludes bibliographical references (page 117-136)Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2020This work presents a radically new computing concept for digital Integrated Circuits (ICs), called Crosstalk Computing. The conventional CMOS scaling trend is facing device scaling limitations and interconnect bottleneck. The other primary concern of miniaturization of ICs is the signal-integrity issue due to Crosstalk, which is the unwanted interference of signals between neighboring metal lines. The Crosstalk is becoming inexorable with advancing technology nodes. Traditional computing circuits always tries to reduce this Crosstalk by applying various circuit and layout techniques. In contrast, this research develops novel circuit techniques that can leverage this detrimental effect and convert it astutely to a useful feature. The Crosstalk is engineered into a logic computation principle by leveraging deterministic signal interference for innovative circuit implementation. This research work presents a comprehensive circuit framework for Crosstalk Computing and derives all the key circuit elements that can enable this computing model. Along with regular digital logic circuits, it also presents a novel Polymorphic circuit approach unique to Crosstalk Computing. In Polymorphic circuits, the functionality of a circuit can be altered using a control variable. Owing to the multi-functional embodiment in polymorphic-circuits, they find many useful applications such as reconfigurable system design, resource sharing, hardware security, and fault-tolerant circuit design, etc. This dissertation shows a comprehensive list of polymorphic logic gate implementations, which were not reported previously in any other work. It also performs a comparison study between Crosstalk polymorphic circuits and existing polymorphic approaches, which are either inefficient due to custom non-linear circuit styles or propose exotic devices. The ability to design a wide range of polymorphic logic circuits (basic and complex logics) compact in design and minimal in transistor count is unique to Crosstalk Computing, which leads to benefits in the circuit density, power, and performance. The circuit simulation and characterization results show a 6x improvement in transistor count, 2x improvement in switching energy, and 1.5x improvement in performance compared to counterpart implementation in CMOS circuit style. Nevertheless, the Crosstalk circuits also face issues while cascading the circuits; this research analyzes all the problems and develops auxiliary circuit techniques to fix the problems. Moreover, it shows a module-level cascaded polymorphic circuit example, which also employs the auxiliary circuit techniques developed. For the very first time, it implements a proof-of-concept prototype Chip for Crosstalk Computing at TSMC 65nm technology and demonstrates experimental evidence for runtime reconfiguration of the polymorphic circuit. The dissertation also explores the application potentials for Crosstalk Computing circuits. Finally, the future work section discusses the Electronic Design Automation (EDA) challenges and proposes an appropriate design flow; besides, it also discusses ideas for the efficient implementation of Crosstalk Computing structures. Thus, further research and development to realize efficient Crosstalk Computing structures can leverage the comprehensive circuit framework developed in this research and offer transformative benefits for the semiconductor industry.Introduction and Motivation -- More Moore and Relevant Beyond CMOS Research Directions -- Crosstalk Computing -- Crosstalk Circuits Based on Perception Model -- Crosstalk Circuit Types -- Cascading Circuit Issues and Sollutions -- Existing Polymorphic Circuit Approaches -- Crosstalk Polymorphic Circuits -- Comparison and Benchmarking of Crosstalk Gates -- Practical Realization of Crosstalk Gates -- Poential Applications -- Conclusion and Future Wor

Embedding Logic and Non-volatile Devices in CMOS Digital Circuits for Improving Energy Efficiency

abstract: Static CMOS logic has remained the dominant design style of digital systems for more than four decades due to its robustness and near zero standby current. Static CMOS logic circuits consist of a network of combinational logic cells and clocked sequential elements, such as latches and flip-flops that are used for sequencing computations over time. The majority of the digital design techniques to reduce power, area, and leakage over the past four decades have focused almost entirely on optimizing the combinational logic. This work explores alternate architectures for the flip-flops for improving the overall circuit performance, power and area. It consists of three main sections. First, is the design of a multi-input configurable flip-flop structure with embedded logic. A conventional D-type flip-flop may be viewed as realizing an identity function, in which the output is simply the value of the input sampled at the clock edge. In contrast, the proposed multi-input flip-flop, named PNAND, can be configured to realize one of a family of Boolean functions called threshold functions. In essence, the PNAND is a circuit implementation of the well-known binary perceptron. Unlike other reconfigurable circuits, a PNAND can be configured by simply changing the assignment of signals to its inputs. Using a standard cell library of such gates, a technology mapping algorithm can be applied to transform a given netlist into one with an optimal mixture of conventional logic gates and threshold gates. This approach was used to fabricate a 32-bit Wallace Tree multiplier and a 32-bit booth multiplier in 65nm LP technology. Simulation and chip measurements show more than 30% improvement in dynamic power and more than 20% reduction in core area. The functional yield of the PNAND reduces with geometry and voltage scaling. The second part of this research investigates the use of two mechanisms to improve the robustness of the PNAND circuit architecture. One is the use of forward and reverse body biases to change the device threshold and the other is the use of RRAM devices for low voltage operation. The third part of this research focused on the design of flip-flops with non-volatile storage. Spin-transfer torque magnetic tunnel junctions (STT-MTJ) are integrated with both conventional D-flipflop and the PNAND circuits to implement non-volatile logic (NVL). These non-volatile storage enhanced flip-flops are able to save the state of system locally when a power interruption occurs. However, manufacturing variations in the STT-MTJs and in the CMOS transistors significantly reduce the yield, leading to an overly pessimistic design and consequently, higher energy consumption. A detailed analysis of the design trade-offs in the driver circuitry for performing backup and restore, and a novel method to design the energy optimal driver for a given yield is presented. Efficient designs of two nonvolatile flip-flop (NVFF) circuits are presented, in which the backup time is determined on a per-chip basis, resulting in minimizing the energy wastage and satisfying the yield constraint. To achieve a yield of 98%, the conventional approach would have to expend nearly 5X more energy than the minimum required, whereas the proposed tunable approach expends only 26% more energy than the minimum. A non-volatile threshold gate architecture NV-TLFF are designed with the same backup and restore circuitry in 65nm technology. The embedded logic in NV-TLFF compensates performance overhead of NVL. This leads to the possibility of zero-overhead non-volatile datapath circuits. An 8-bit multiply-and- accumulate (MAC) unit is designed to demonstrate the performance benefits of the proposed architecture. Based on the results of HSPICE simulations, the MAC circuit with the proposed NV-TLFF cells is shown to consume at least 20% less power and area as compared to the circuit designed with conventional DFFs, without sacrificing any performance.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Drug Eluting Stent Implantation for High Risk Patients and Novel Technologies in Percutaneous Coronary Intervention

Percutaneous coronary intervention is a major treatment strategy for patients with coronary artery disease, and currently coronary stents are widely used in the world.1 Although stent implantation itself has shown to reduce restenosis by preventing both early elastic recoil and late vascular remodeling compared to balloon angioplasty, in-stent restenosis (ISR) still occurs in 10-40% of patients and has been the ‘Achilles’ heel’ of coronary interventions, frequently resulting in repeated revascularization.2,3 Restenosis after coronary stenting occurs secondary to the accumulation of smooth muscle cells and extracellular matrix proteoglycans.4 Despite the sophistication of the new techniques and enormous advance in devices, ISR requiring repeat procedure has been considered as a main limitation of coronary stenting. The advent of drug eluting stents (DES), which consist of a drug (immunosuppressive or antiproliferative drug), a polymer and a metallic platform, has revolutionized the practice of interventional cardiology by significantly reducing the rates of restenosis and repeat revascularization as compared to bare metal stents.5 After the first approval of DES, a large number of patients with coronary artery disease have undergone percutaneous revascularization with DES. However, many trials conducted in the ‘real world’ showed that the problem of restenosis was not completely resolved and still persists. Effect of DES for patients at high risk for ISR, such as acute myocardial infarction, small coronary vessels, aorto-ostial lesions, or lesions of chronic total occlusion (Part 1 of this thesis), have not been fully investigated. In addition, certain potential safety concerns regarding the widespread use of DES have arisen. The most notable drawback of DES is that they could increase the risk of thrombotic complication, especially late stent thrombosis6, although its incidence is low.7 The increased risk of thrombosis with DES utilization may be associated with altered endothelial function8 and/or delayed vascular healing9 induced by cytotoxic and cytostatic drug use. Localized hypersensitivity reactions to the polymer coating of DES and drug itself may also contribute to stent thrombosis.10 To retain the positive clinical aspects of DES and overcome their drawbacks, new concept stents have been developed (Part 2 of this thesis)

Novel Applications of Terahertz Quantum Cascade Lasers: Gas Spectroscopy, Active Control & Nearfield Imaging

Since the advent of Terahertz (THz) quantum cascade lasers (QCLs) in 2002, they have seen significant improvement in output power, operating temperature, and spectral coverage as well as having been widely applied to astronomical applications, imaging, and spectroscopy because of their high output power and narrow spectral linewidth. In this work, three techniques, self-mixing gas spectroscopy, THz amplitude modulation and THz nearfield imaging, will be experimentally studied and demonstrated. These techniques can either expand or increase the efficiency of their corresponding applications using other techniques. The dissertation starts with a brief introduction of the basic knowledge of THz QCLs and some characterization methods for a THz system, as well as a summary of their main applications and their current capabilities. When the lasing of a THz QCL is suppressed, it becomes a quantum cascade amplifier (QCA), which compared with a THz QCL can enhance the sensitivity in both spectroscopy and imaging applications. A THz QCA has been achieved by adhering an antireflection-coated Si lens to the QCL facet and is then used as the source for THz gas spectroscopy based on a self-mixing effect, in which the THz QCL functions as both the light source and the detector. This offers an approach to achieving a compact spectroscopy system with a fast response. For spectroscopy, communication and astronomical applications, the ability to actively control the amplitude of the THz radiation is desired. This has been demonstrated with a graphene loaded metamaterial device, with which and a PID feedback loop, the output power fluctuation of a THz QCL is reduced from 1.52% to 0.043% of the total power. An amplitude stabilised THz source is also essential for high resolution THz imaging, where amplitude fluctuations will distort the acquired THz images. A scattering type nearfield microscope (s-SNOM) with a better than λ/1000 resolution has been demonstrated with a tuning fork based atomic force microscope (AFM) and a partially suppressed THz QCL. The detection scheme is also harnessing the self-mixing effect. Compared with conventional detection methods, this can give a fast response and high sensitivity, which are essential for high-speed high-resolution imaging. The performance of this home-built THz s-SNOM has then been significantly improved by vibration isolation and electronic noise reduction and it has been used to examine a variety of samples. It is able to reveal the plasmonic resonance of resonant structures, spatially map the electric field distribution on a metamaterial device and image subsurface plasmons. By using tips of different materials, it has also been found that a gold coating can improve the THz sensitivity of the system. Afterwards, to optimise the design of metamaterials, a special metasurface has been designed to study the influence of the geometric parameters on the optical performance of it. This can be achieved by probing the electric field distribution of the metasurface with the THz s-SNOM. The dissertation is then concluded with all the results obtained and a brief overview of what can be done in the future in related research fields

Modeling Stented Coronary Arteries: Where We are, Where to Go

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