A Novel Differential Ramp Generator Circuit with PVT Compensation Structure

Applications like counter ADC demanded accurate ramp signal with low power dissipation. This paper presents a novel approach of low power differential ramp generator with negative feedback for the compensation of the variations in process, voltage, and temperature (PVT). The derived equations of the proposed ramp generator circuit show that PVT compensation is enhanced significantly. Additionally, the circuit design and simulations were done in TSMC 0.18-μm CMOS technology. The Monte Carlo simulation results and corner analysis show that the linearity of the ramp signal is about 9-bit while power dissipation of the circuit is about 2.61μW

Design and debugging of multi-step analog to digital converters

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has forced the A/D converter interface to reside on the same silicon in complex mixed-signal ICs containing mostly digital blocks for DSP and control. However, specifications of the converters in various applications emphasize high dynamic range and low spurious spectral performance. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons. Additionally, as CMOS integrated circuits are accomplishing unprecedented integration levels, potential problems associated with device scaling – the short-channel effects – are also looming large as technology strides into the deep-submicron regime. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. Practical realizations show the trend that to a first order, converter power is directly proportional to sampling rate. However, power dissipation required becomes nonlinear as the speed capabilities of a process technology are pushed to the limit. Pipeline and two-step/multi-step converters tend to be the most efficient at achieving a given resolution and sampling rate specification. This thesis is in a sense unique work as it covers the whole spectrum of design, test, debugging and calibration of multi-step A/D converters; it incorporates development of circuit techniques and algorithms to enhance the resolution and attainable sample rate of an A/D converter and to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover and compensate for the errors continuously. The power proficiency for high resolution of multi-step converter by combining parallelism and calibration and exploiting low-voltage circuit techniques is demonstrated with a 1.8 V, 12-bit, 80 MS/s, 100 mW analog to-digital converter fabricated in five-metal layers 0.18-µm CMOS process. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. Microscopic particles present in the manufacturing environment and slight variations in the parameters of manufacturing steps can all lead to the geometrical and electrical properties of an IC to deviate from those generated at the end of the design process. Those defects can cause various types of malfunctioning, depending on the IC topology and the nature of the defect. To relive the burden placed on IC design and manufacturing originated with ever-increasing costs associated with testing and debugging of complex mixed-signal electronic systems, several circuit techniques and algorithms are developed and incorporated in proposed ATPG, DfT and BIST methodologies. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. With the use of dedicated sensors, which exploit knowledge of the circuit structure and the specific defect mechanisms, the method described in this thesis facilitates early and fast identification of excessive process parameter variation effects. The expectation-maximization algorithm makes the estimation problem more tractable and also yields good estimates of the parameters for small sample sizes. To allow the test guidance with the information obtained through monitoring process variations implemented adjusted support vector machine classifier simultaneously minimize the empirical classification error and maximize the geometric margin. On a positive note, the use of digital enhancing calibration techniques reduces the need for expensive technologies with special fabrication steps. Indeed, the extra cost of digital processing is normally affordable as the use of submicron mixed signal technologies allows for efficient usage of silicon area even for relatively complex algorithms. Employed adaptive filtering algorithm for error estimation offers the small number of operations per iteration and does not require correlation function calculation nor matrix inversions. The presented foreground calibration algorithm does not need any dedicated test signal and does not require a part of the conversion time. It works continuously and with every signal applied to the A/D converter. The feasibility of the method for on-line and off-line debugging and calibration has been verified by experimental measurements from the silicon prototype fabricated in standard single poly, six metal 0.09-µm CMOS process

Time interleaved counter analog to digital converters

The work explores extending time interleaving in A/D converters, by applying a high-level of parallelism to one of the slowest and simplest types of data-converters, the counter ADC. The motivation for the work is to realise high-performance re-configurable A/D converters for use in multi-standard and multi-PHY communication receivers with signal bandwidths in the 10s to 100s of MHz. The counter ADC requires only a comparator, a ramp signal, and a digital counter, where the comparator compares the sampled input against all possible quantisation levels sequentially. This work explores arranging counter ADCs in large time-interleaved arrays, building a Time Interleaved Counter (TIC) ADC. The key to realising a TIC ADC is distributed sampling and a global multi-phase ramp generator realised with a novel figure-of-8 rotating resistor ring. Furthermore Counter ADCs allow for re-configurability between effective sampling rate and resolution due to their sequential comparison of reference levels in conversion. A prototype TIC ADC of 128-channels was fabricated and measured in 0.13μm CMOS technology, where the same block can be configured to operate as a 7-bit 1GS/s, 8-bit 500MS/s, or 9-bit 250MS/s dataconverter. The ADC achieves a sub 400fJ/step FOM in all modes of configuration

High Temperature Silicon Carbide Mixed-signal Circuits for Integrated Control and Data Acquisition

Wide bandgap semiconductor materials such as gallium nitride (GaN) and silicon carbide have grown in popularity as a substrate for power devices for high temperature and high voltage applications over the last two decades. Recent research has been focused on the design of integrated circuits for protection and control in these wide bandgap materials. The ICs developed in SiC and GaN can not only complement the power devices in high voltage and high frequency applications, but can also be used for standalone high temperature control and data acquisition circuitry. This dissertation work aims to explore the possibilities in high temperature and wide bandgap circuit design by developing a host of mixed-signal circuits that can be used for control and data acquisition. These include a family of current-mode signal processing circuits, general purpose amplifiers and comparators, and 8-bit data converters. The signal processing circuits along with amplifiers and comparators are then used to develop an integrated mixed-signal controller for a DC-DC flyback converter in a microinverter application. The 8-bit SAR ADC and the 8-bit R-2R ladder DAC open up the possibility of a remote data acquisition and control system in high temperature environments. The circuits and systems presented here offer a gateway to great opportunities in high temperature and power electronics ICs in SiC

DIGITALLY ASSISTED TECHNIQUES FOR NYQUIST RATE ANALOG-to-DIGITAL CONVERTERS

With the advance of technology and rapid growth of digital systems, low power high speed analog-to-digital converters with great accuracy are in demand. To achieve high effective number of bits Analog-to-Digital Converter(ADC) calibration as a time consuming process is a potential bottleneck for designs. This dissertation presentsa fully digital background calibration algorithm for a 7-bit redundant flash ADC using split structure and look-up table based correction. Redundant comparators are used in the flash ADC design of this work in order to tolerate large offset voltages while minimizing signal input capacitance. The split ADC structure helps by eliminating the unknown input signal from the calibration path. The flash ADC has been designed in 180nm IBM CMOS technology and fabricated through MOSIS. This work was supported by Analog Devices, Wilmington,MA. While much research on ADC design has concentrated on increasing resolution and sample rate, there are many applications (e.g. biomedical devices and sensor networks) that do not require high performance but do require low power energy efficient ADCs. This dissertation also explores on design of a low quiescent current 100kSps Successive Approximation (SAR) ADC that has been used as an error detection ADC for an automotive application in 350nm CD (CMOS-DMOS) technology. This work was supported by ON Semiconductor Corp, East Greenwich,RI

8-bit 1 Gs/s Adc Architecture And 4-bit Flash Adc For +10 Gs/s Time Interleaved Adc In 65nm Cmos Technology

Tez (Yüksek Lisans) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2015Thesis (M.Sc.) -- İstanbul Technical University, Instıtute of Science and Technology, 2015Haberleşme sistemlerinin veri aktarım sıklıkları ve bant genişlikleri sürekli olarak artmaktadır. Sayısal yarıiletken teknolojilerindeki gelişmeler, haberleşme sistemlerindeki işaret işleme kısımlarını sayısal domenine almıştır. Sayısal işaret işlemenin avantajları, ideal olmayan durumlara yüksek tolerans, gerçekleme kolaylığı, bir fonksiyonu gerçeklemek için gereken alanın dolayısıyla maliyetin düşük olması ve yeni teknolojilere taşınabilme olarak sayılabilir. Bu avantajlardan faydalanmak için analog işaretleri sayısal domene almada köprü görevi görecek yüksek hızlı analog-sayısal dönüştürücülere(ADC) ihtiyaç vardır. Kablolu ve kablosuz haberleşme teknolojilerinde 10 GHz'yi de aşan bant genişlikleri tek kanallı ADCleri bu iş için elverişsiz kılmaktadır. Zaman aralıklı ADCler gerek ulaşabilecekleri dönüştürme hızı gerek güç verimliliği açısından iyi bir aday olarak karşımıza çıkar. Zaman aralıklama, tek kanallı eş ADClerin sıra ile kullanılması esasına dayanmaktadır. Sıradaki örneği alan ADC, sıra tekrar kendisine gelene kadar bu örneği dönüştürür. Dolayısıyla toplam dönüştürme hızı, tek bir dönüştürücünün hızı ile kanal sayısının çarpımı kadar olmaktadır. Bu şekilde yüksek dönüştürme hızları elde edilebilir. Ayrıca bu şekilde tek kanal ADCler daha fazla hız elde etmek için güç bakımından verimsiz oldukları noktalara itilmez ve daha verimli yapılar ortaya çıkar. Zaman aralıklı ADClerdeki kanal uyumsuzlukları performansı düşürmektedir. Bu hatalar temel olarak dengesizlik, kazanç ve zamanlama uyumsuzluklarından ileri gelmektedir. Zamanlama hataları kestirilmeleri ve düzeltilmeleri noktasında diğerlerinden daha zorludur ve bu durum yüksek frekanslarda daha da zorlaşmaktadır. Zaman aralıklı ADClerdeki zamanlama hatalarının kestirilmeleri ve düzeltilmeleri güncel bir araştırma konusu teşkil etmektedir. Hataların kalibrasyonu ön planda veya arka planda yapılabilir. Arka planda yapılan kalibrasyon sistemin işlerliği ile ilgili herhangi bir sıkıntı yaratmaması ve değişen çevre şartlarına uyum sağlayabilme esnekliği açısından daha avantajlıdır. Zaman aralıklama hataları frekans spektrumunda çıkıntılar(spur) oluşturmaktadır. Bu çıkıntılar, güçlü olmaları durumunda alıcı kısmındaki devreleri sıkıştırma noktasına iterek modülasyonlu işaretlerin sezilmesini zorlaştırabilir veya giriş işaretini tamamen engelleyebilirler. Dolayısıyla kanal uyumsuzluk hataları özellikle kablosuz haberleşme sistemleri için sorun teşkil etmektedir. Bu sorunlardan kurtulmak için kanalları rastgele kullanmaya dayanan bir teknik önerilmiştir. Bu teknik ile kanallardan kaynaklanan hatalar çıkışa rastgele bir sırayla etki yaptıklarından gürültü gibi bir karaktere geçerler. Dolayısıyla frekans spektrumundaki çıkıntılar söndürülmüş olur. Tekniğin bir diğer avantajı arka planda çalışmasıdır. Ancak dikkat edilmelidir ki bu teknik bir hata düzeltme tekniği değildir, dolayısıyla sistemin işaretgürültü oranını iyileştirmemektedir. Kanal uyumsuzluk hatalarının kestirilmesi gibi, saat işaretlerinin dağıtılması da artan kanal sayısı ile zorlaşmaktadır. Ayrıca yüksek kanal sayısına sahip olan zaman aralıklı ADClerde saat işareti dağıtımının tükettiği güç yüksek seviyelere ulaşabilir. Belli bir dönüştürme hızı için kanal sayısını düşük tutmak ise kanal ADClerinin dönüştürme hızlarını arttırmak ile mümkündür. ADClerin hızları yüksek tutulurken aynı zamanda güç verimliliği de yüksek tutulmalıdır. Bu hedefler doğrultusunda 8-bit 1 GS/s bir çevrimde birden fazla bit dönüştüren bir SAR ADC yapısı önerilmiştir. Bir çevrimde birden fazla bit dönüştüren SAR ADCler, tek kanalda yüksek hızlara çıkmak konusunda sıkça kullanılan bir yöntem olarak karşımıza çıkmaktadır. Bunun yanında ilk üç en anlamlı bit bir flash ADC ile dönüştürüldüğünden önemli hız kazanımları elde edilir. Flash ADC çıkışında bir kod çözücü yapısı kullanılmaması da zaman kazanımında etkilidir. Önerilen ADC yapısında özgün bir dönüştürme algoritması kullanılmaktadır. Algoritma temel olarak, dönüştürme fazlarına fazladan seviyeler eklemek ve fazların aralıklarını kesiştirmek sureti ile devre bloklarının hata toleranslarını arttırmasına dayanmaktadır. Bu nedenle herhangi bir kalibrasyon sistemine ihtiyaç duyulmaz dolayısıyla güç tüketimi azaltılabilir. Bu yapının gerçeklenebilmesi için çoklu seviye üreten bir ön kuvvetlendirici önerilmiştir. Önerilen ön kuvvetlendirici yapısı nedeniyle, algoritmadaki farklı fazlar için tek bir ön kuvvetlendirici kullanılabilmektedir. Bu sayede farklı ön kuvvetlendiricilerden kaynaklanacak dengesizlik uyumsuzluklarının da önüne geçilmiş olur. Yüksek hızlı veri dönüştürücülerin gerçeklenmesindeki en etkili devre bloğu, kendisi de 1 bitlik bir ADC olarak sayılabilecek karşılaştırıcı devreleridir. Karşılaştırıcı devresinin hızı, doğruluğu ve güç tüketimi bir ADCnin ilgili performans parametrelerini doğrudan etkilemektedir. Yüksek karşılaştırma hızlı özgün bir gömülü ön kuvvetlendiricili karşılaştırıcı devre önerilmiştir. Yapı geleneksel dinamik sezme kuvvetlendiricisi devresi temel alınarak tasarlanmıştır. Ek olarak giriş farksal kuvvetlendirici bölümüne bir statik akım kaynağı bağlanmıştır. Bu şekilde dinamik karşılaştırıcı yapısına ön kuvvetlendirici gömülmüş olur. Yapı geleneksel yapılara nazaran, hız, dengesizlik, güç tüketimi ve geri tepme gürültüsü açısından iyileştirmeler içermektedir. 8-bit 1 GS/s bir çevrimde birden fazla bit dönüştüren SAR ADC yapısı, ilk 3 biti olabildiğince hızlı dönüştürmek için bir flash ADC yapısı kullanmaktadır. Flash ADC yapılarının önemli hız avantajlarına rağmen, karşılaştırıcı devrelerin dengesizlik ve geri tepme gürültüsü performansı düşürmektedir. Önerilen gömülü ön kuvvetlendiricili karşılaştırıcı devresi dengesizlik performansını ve geri tepme gürültüsünü iyileştirmektedir. Ancak geri tepme gürültüsünden kaynaklanan hataları tam olarak çözmek adına, referans gerilimleri de giriş işaretleri gibi örneklenebilir. Bu teknik ile karşılaştırıcı geri tepme gürültüsünün giriş ve referans gerilimi üzerindeki etkisi eşitlenmekte ve geri tepme gürültüsünün etkisi bertaraf edilmektedir. ADC girişleri örneklenerek geldiğinden ve örnekleme devrelerindeki bir hata doğrudan ADCye iletileceğinden bu devrelerin performansı çok önemlidir. Çapraz bağlamalı anahtar tekniği kullanılarak anahtarların doğrusallığı iyileştirilmiştir. Aynı zamanda çapraz bağlama tekniği anahtar yük enjeksiyonu hatasını giriş işaretinden bağımsız hale getirmektedir. Bu durum, yukarıda bahsedilen referans örnekleme tekniği ile birleştirildiğinde flash ADC için önemli bir doğruluk iyileştirmesi sağlamaktadır. ADC blokları ST Microelectronics 65 nm CMOS teknolojisinde tasarlanmış ve serimleri yapılmıştır. Serim sonrası benzetim sonuçları tasarımların ve kullanılan tekniklerin doğruluğunu göstermektedir. Tasarlanan ADC Haziran 2015'de üretime yollanmıştır. Kasım 2015'de ölçümlere başlanması planlanmaktadır.Data rate of communication systems constantly increasing . Rapid scaling of digital semiconductor technologies has moved the signal processing of these systems to digital domain. Therefore high-speed ADCs are required to form the bridge to take the analog signals in digital domain. Data rates exceeding 10 Gbps makes the use of single channel ADCs unfeasible on this purpose. A power efficient solution is time-interleaving. Time-interleaving relaxes the speed requirements on single channel ADCs and lets designers to focus on power efficiency of the ADC. Channel mismatches in time-interleaved ADCs causes performance degradation. Errors arise mainly due to offset, gain and timing mismatch of channels. Among them, timing error is the most problematic since estimation of timing errors becomes more cumbersome in high-frequencies. Estimation and correction of timing errors in time-interleaved ADCs are hot topics of research. Calibration of errors can be on background or on foreground. Background calibration is more desirable since it allows system to adapt to changing conditions while not hindering the operation of the ADC. Time interleaving errors generate spurs on the spectrum. Spurs are problematic for the wireless communication systems, since they may block the input signal. In order to extinguish the spurs a channel randomization technique is proposed. Technique is based on randomly taking one of the ADC channels to make the errors of the channels noise-like term. It is advantageous since it works on background. Technique maintains a spur-free spectrum however does not improve the SNR of the system. Estimation of channel mismatch errors and clock distribution in a time-interleaved ADC becomes tedious as the number of channels increase. In order to keep the channel number low, channels should be fast while being power efficient. To satisfy this task, an 8-bit 1 GS/s multi-bit per cycle ADC is proposed. ADC employs a novel search algorithm based on redundancy. No calibration scheme required thanks to the algorithm therefore the power efficiency of the system can be increased. In order to realize the multi-bit per cycle structure, a multiple-threshold generation preamp is proposed. Comparators are the most important part of an ADC. Comparator specifications such as speed, accuracy and power consumption directly affect the relative specifications of the whole ADC. A novel latch with embedded preamp is proposed. Novel structure has latch regeneration time, offset, power consumption and kickback noise improvements over the conventional structures. 8-bit 1 GS/s multi-bit per cycle SAR ADC employs a flash ADC to perform the coarse conversion benefit from its speed. Although flash ADCs are fast, offset and kickback noise of comparators can penalize their accuracy. Proposed latch with embedded preamp improves the offset performance. To solve the kickback issue, reference voltages of the flash ADC are sampled. This technique is based on equalizing the kickback for both input and reference voltages therefore eliminating the effect. Sampling network of the ADC is critically important since any error made in the sampling phase directly passes to the ADC. Bootstrapped switches are used to improve the linearity of the switches. By using bootstrap switches, charge injection can be made signal independent. If it is combined with the reference sampling technique used in flash ADC, effects of charge injection can be diminished significantly. ADC blocks are designed and laid out in ST Microlectronics 65 nm process. Postlayout simulations have proven the efectiveness of the proposed techniques and blocks. Tape-out was done in July 2015. Measurements is expected to take place in November 2015.Yüksek LisansM.Sc

Digital Background Self-Calibration Technique for Compensating Transition Offsets in Reference-less Flash ADCs

This Dissertation focusses on proving that background calibration using adaptive algorithms are low-cost, stable and effective methods for obtaining high accuracy in flash A/D converters. An integrated reference-less 3-bit flash ADC circuit has been successfully designed and taped out in UMC 180 nm CMOS technology in order to prove the efficiency of our proposed background calibration. References for ADC transitions have been virtually implemented built-in in the comparators dynamic-latch topology by a controlled mismatch added to each comparator input front-end. An external very simple DAC block (calibration bank) allows control the quantity of mismatch added in each comparator front-end and, therefore, compensate the offset of its effective transition with respect to the nominal value. In order to assist to the estimation of the offset of the prototype comparators, an auxiliary A/D converter with higher resolution and lower conversion speed than the flash ADC is used: a 6-bit capacitive-DAC SAR type. Special care in synchronization of analogue sampling instant in both ADCs has been taken into account. In this thesis, a criterion to identify the optimum parameters of the flash ADC design with adaptive background calibration has been set. With this criterion, the best choice for dynamic latch architecture, calibration bank resolution and flash ADC resolution are selected. The performance of the calibration algorithm have been tested, providing great programmability to the digital processor that implements the algorithm, allowing to choose the algorithm limits, accuracy and quantization errors in the arithmetic. Further, systematic controlled offset can be forced in the comparators of the flash ADC in order to have a more exhaustive test of calibration

Efficient Continuous-Time Sigma-Delta Converters for High Frequency Applications

Over the years Continuous-Time (CT) Sigma-Delta (ΣΔ) modulators have received a lot of attention due to their ability to efficiently digitize a variety of signals, and suitability for many different applications. Because of their tolerance to component mismatch, the easy to drive input structure, as well as intrinsic anti-aliasing filtering and noise shaping abilities, CTΣΔ modulators have become one of the most popular data-converter type for high dynamic range and moderate/wide bandwidth. This trend is the result of faster CMOS technologies along with design innovations such as better architectures and faster amplifiers. In other words, CTΣΔ modulators are starting to offer the best of both worlds, with high resolution and high bandwidth. This dissertation focuses on the bandwidth and resolution of CTΣΔ modulators. The goal of this research is to use the noise shaping benefits of CTΣΔ modulators for different wireless applications, while achieving high resolution and/or wide bandwidth. For this purpose, this research focuses on two different application areas that demand speed and resolution. These are a low-noise high-resolution time-to-digital converter (TDC), ideal for digital phase lock loops (PLL), and a very high-speed, wide-bandwidth CTΣΔ modulator for wireless communication. The first part of this dissertation presents a new noise shaping time-to-digital converter, based on a CTΣΔ modulator. This is intended to reduce the in-band phase noise of a high frequency digital phase lock loop (PLL) without reducing its loop bandwidth. To prove the effectiveness of the proposed TDC, 30GHz and a 40GHz fractional-N digital PLL are designed as a signal sources for a 240GHz FMCW radar system. Both prototypes are fabricated in a 65nm CMOS process. The standalone TDC achieves 81dB dynamic range and 13.2 equivalent number of bits (ENOB) with 176fs integrated-rms noise from 1MHz bandwidth. The in-band phase noise of the 30GHz digital fractional-N PLL is measured as -87dBc/Hz at a 100kHz offset which is equivalent to -212.6dBc/Hz2 normalized in-band phase noise. The second part of this dissertation focuses on high-speed (GS/s) CTΣΔ modulators for wireless communication, and introduces a new time-interleaved reference data weighted averaging (TI-RDWA) architecture suitable for GS/s CTΣΔ modulators. This new architecture shapes the digital-to-analog converter (DAC) mismatch effects in a CTΣΔ modulator at GS/s operating speeds. It allows us to use smaller DAC unit sizes to reduce area and power consumption for the same bandwidth. The prototype 5GS/s CTΣΔ modulator with TI-RDWA is fabricated in 40nm CMOS and it achieves 156MHz bandwidth, 70dB dynamic range, 84dB SFDR and a Schreier FoM of 158.3dB.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/138763/1/bdayanik_1.pd

Design of high speed folding and interpolating analog-to-digital converter

High-speed and low resolution analog-to-digital converters (ADC) are key elements in the read channel of optical and magnetic data storage systems. The required resolution is about 6-7 bits while the sampling rate and effective resolution bandwidth requirements increase with each generation of storage system. Folding is a technique to reduce the number of comparators used in the flash architecture. By means of an analog preprocessing circuit in folding A/D converters the number of comparators can be reduced significantly. Folding architectures exhibit low power and low latency as well as the ability to run at high sampling rates. Folding ADCs employing interpolation schemes to generate extra folding waveforms are called "Folding and Interpolating ADC" (F&I ADC). The aim of this research is to increase the input bandwidth of high speed conversion, and low latency F&I ADC. Behavioral models are developed to analyze the bandwidth limitation at the architecture level. A front-end sample-and-hold unit is employed to tackle the frequency multiplication problem, which is intrinsic for all F&I ADCs. Current-mode signal processing is adopted to increase the bandwidth of the folding amplifiers and interpolators, which are the bottleneck of the whole system. An operational transconductance amplifier (OTA) based folding amplifier, current mirror-based interpolator, very low impedance fast current comparator are proposed and designed to carry out the current-mode signal processing. A new bit synchronization scheme is proposed to correct the error caused by the delay difference between the coarse and fine channels. A prototype chip was designed and fabricated in 0.35μm CMOS process to verify the ideas. The S/H and F&I ADC prototype is realized in 0.35μm double-poly CMOS process (only one poly is used). Integral nonlinearity (INL) is 1.0 LSB and Differential nonlinearity (DNL) is 0.6 LSB at 110 KHz. The ADC occupies 1.2mm2 active area and dissipates 200mW (excluding 70mW of S/H) from 3.3V supply. At 300MSPS sampling rate, the ADC achieves no less than 6 ENOB with input signal lower than 60MHz. It has the highest input bandwidth of 60MHz reported in the literature for this type of CMOS ADC with similar resolution and sample rate