Wafer-level packaged RF-MEMS switches fabricated in a CMOS fab

Reports on wafer-level packaged RF-MEMS switches fabricated in a commercial CMOS fab. Switch fabrication is based on a metal surface micromachining process. A novel wafer-level packaging scheme is developed, whereby the switches are housed in on-chip sealed cavities using benzocyclobutene (BCB) as the bonding and sealing material. Measurements show that the influence of the wafer-level package on the RF performance can be made very small.\ud \u

Performance Comparison of Phase Change Materials and Metal-Insulator Transition Materials for Direct Current and Radio Frequency Switching Applications

Advanced understanding of the physics makes phase change materials (PCM) and metal-insulator transition (MIT) materials great candidates for direct current (DC) and radio frequency (RF) switching applications. In the literature, germanium telluride (GeTe), a PCM, and vanadium dioxide (VO2), an MIT material have been widely investigated for DC and RF switching applications due to their remarkable contrast in their OFF/ON state resistivity values. In this review, innovations in design, fabrication, and characterization associated with these PCM and MIT material-based RF switches, have been highlighted and critically reviewed from the early stage to the most recent works. We initially report on the growth of PCM and MIT materials and then discuss their DC characteristics. Afterwards, novel design approaches and notable fabrication processes; utilized to improve switching performance; are discussed and reviewed. Finally, a brief vis-á-vis comparison of resistivity, insertion loss, isolation loss, power consumption, RF power handling capability, switching speed, and reliability is provided to compare their performance to radio frequency microelectromechanical systems (RF MEMS) switches; which helps to demonstrate the current state-of-the-art, as well as insight into their potential in future applications

Master of Science

thesisPower consumption is a major concern in the present chip design industry. Complementary Metal Oxide Semiconductor (CMOS) technology scaling has led to an exponential increase in the leakage power. The excessive power dissipation can result in more heat generation, which in turn increases the temperature. According to Intel's source, power density increased to a value of 1000 W/cm2 and is approaching the value which is equal to the radiation from the sun's surface (10000 W/cm2). This leads to reliability issues in nanometer-scale CMOS as Silicon starts melting at 1687K. To resolve this issue, we introduce a novel architecture to design nanoelectromechanical switches and implementation results with virtually zero leakage current, ~1 V operation voltage, ~1 GHz resonant frequency and nanometer-scale footprint. Microelectromechanical Switches (MEMS) have very low "on" and very high "off" resistances. Their switching voltages are usually high (5-50 V), switching speeds are usually low (1 MHz) and their footprints tend to be very large (many um2). We have designed and fabricated devices with very low actuation voltages and very high speed using tuning fork geometry compatible with conventional CMOS fabrication technologies. This unique switch geometry decreases the actuation voltage by a factor of 1.4 and doubles the switching speed. It consists of a cantilever beam that acts as a ground plane. Upon actuation, both the ground plane and the switch's main beam move towards each other that makes the center of mass stationary during switching and thus, the switching speed doubles

Programmable latching probe microstructures for wafer testing applications

The objective of this thesis is to design a programmable wafer testing array on a single chip based on micro electromechanical systems (MEMS) and VLSI. The wafer-scale integration in this thesis is a programmable array of test probes that are used for engineering test of VLSI and ULSI silicon integrated circuits at the wafer level. This consists of two subsystems (1) the VLSI address circuits used for addressing and controlling the MEMS on the chip and (2) the latching probe MEMS microstructure array that actuates into position for testing VLSI wafers. Each of the subsystems have been designed, analyzed and simulated separately. These structures were then integrated into a demonstration 4x4 array forming a programmable probe card. A 3-micrometer critical dimension is used for both the VLSI CMOS and the MEMS physical design layouts. The fabrication technique for the MEMS microstructure is detailed. A standard 12-mask CMOS technology is used for the fabrication of the address circuits

Doctor of Philosophy

dissertationThis dissertation describes the design, fabrication, testing, reliability, and harsh environment performance of single-device Micro-electro-mechanical-system (MEMS)- based digital logic gates, such as XOR and AND, for applications in ultra-low-power computation in unforgiving settings such as high ionizing radiation and high temperatures. Within the scope of this dissertation are several significant contributions. First, this work was the first ever to report the evolution in logic design architecture from a CMOS-paradigm to a MEMS architecture utilizing a single functional device per logic, as opposed to multiple relays per logic. This novel approach reduces the number of devices needed to implement a logic function by approximately 10X, leading to better reliability, yield, speed, and overall better characteristics (subthreshold characteristics, smaller turn-on/off voltage variations, etc.) and it simplifies implementation of MEMSbased circuits. The logic gates illustrate ~1.5V turn-on voltage at 5MHz with >109 cycles of reliable operations and low operational power consumption (leakage current and power <10-9A, <1^W). Second, this work is the first ever to report an intensive study on the cycle-bycycle evolution of contact resistance (Rc) up to 100,000 cycles, on materials such as, Ir, Pt, W, Ni, Cr, Ti, Cu, Al, and graphite, which are materials commonly used in MEMS switches. Adhesion forces between contacts were also studied using a contact-modeAFM, force vs. displacement, experiment. Results show that materials with high Young's modulus, high melting temperatures, and high density show low initial contact resistances and low adhesion forces (such as Ir, Pt, and W). Third, the devices were interrogated separately in harsh environments where they were exposed to high doses of ionizing radiation (90kW) in a nuclear reactor for a prolonged time (120 min) and, separately, at high temperatures (409K). Here, results show that solid-state devices begin to deteriorate almost immediately to a point where their gate can no longer control the drain-to-source current, whereas MEMS switches survive such ionizing radiation and temperatures portraying clear ON and OFF states for far longer. In terms of the applications empowered and the breadth of topics covered to accomplish these results, the work presented here demonstrates significant contributions to an important and developing branch of engineering

Design for reliability applied to RF-MEMS devices and circuits issued from different TRL environments

Ces travaux de thèse visent à aborder la fiabilité des composants RF-MEMS (commutateurs en particulier) pendant la phase de conception en utilisant différents approches de procédés de fabrication. Ça veut dire que l'intérêt est focalisé en comment éliminer ou diminuer pendant la conception les effets des mécanismes de défaillance plus importants au lieu d'étudier la physique des mécanismes. La détection des différents mécanismes de défaillance est analysée en utilisant les performances RF du dispositif et le développement d'un circuit équivalent. Cette nouvelle approche permet à l'utilisateur final savoir comment les performances vont évoluer pendant le cycle de vie. La classification des procédés de fabrication a été faite en utilisant le Technology Readiness Level du procédé qui évalue le niveau de maturité de la technologie. L'analyse de différentes approches de R&D est décrite en mettant l'accent sur les différences entre les niveaux dans la classification TRL. Cette thèse montre quelle est la stratégie optimale pour aborder la fiabilité en démarrant avec un procédé très flexible (LAAS-CNRS comme exemple de baisse TRL), en continuant avec une approche composant (CEA-Leti comme moyenne TRL) et en finissant avec un procédé standard co-intégré CMOS-MEMS (IHP comme haute TRL) dont les modifications sont impossibles.This thesis is intended to deal with reliability of RF-MEMS devices (switches, in particular) from a designer point of view using different fabrication process approaches. This means that the focus will be on how to eliminate or alleviate at the design stage the effects of the most relevant failure mechanisms in each case rather than studying the underlying physics of failure. The detection of the different failure mechanisms are investigated using the RF performance of the device and the developed equivalent circuits. This novel approach allows the end-user to infer the evolution of the device performance versus time going one step further in the Design for Reliability in RF-MEMS. The division of the fabrication process has been done using the Technology Readiness Level of the process. It assesses the maturity of the technology prior to incorporating it into a system or subsystem. An analysis of the different R&D approaches will be presented by highlighting the differences between the different levels in the TRL classification. This thesis pretend to show how reliability can be improved regarding the approach of the fabrication process starting from a very flexible one (LAAS-CNRS as example of low-TRL) passing through a component approach (CEA-Leti as example of medium-TRL) and finishing with a standard co-integrated CMOS-MEMS process (IHP example of high TRL)

Materials selection and design of microelectrothermal bimaterial actuators

A common form of MEMS actuator is a thermally actuated bimaterial, which is easy to fabricate by surface micromachining and permits out of plane actuation, which is otherwise difficult to achieve. This paper presents an analytical framework for the design of such microelectrothermal bimaterial actuators. Mechanics relationships for a cantilever bimaterial strip subjected to a uniform temperature were applied to obtain expressions for performance metrics for the actuator, i.e., maximum work/volume, blocked (force) moment, and free-end (displacement) slope. Results from finite-element analysis and closed form relations agree well to within 1%. The optimal performance for a given pair of materials and the corresponding thickness ratio were determined. Contours of equal performance corresponding to commonly used substrates (e.g., Si, SiO2) were plotted in the domain of governing material properties (thermal expansion coefficient and Young's modulus) to identify candidate materials for further development. These results and the accompanying methodology provide a rational basis for comparing the suitability of "standard" materials for microelectrothermal actuators, as well as identifying materials that might be suitable for further research

Performance Comparison between Two Electrodes and Three Electrodes MEMS Capacitive Switch using Architect Coventorware

This paper presents the electromechanical and RF performance comparison between two electrodes and three electrodes MEMS capacitive switch using Architect Coventorware. The important of this study is to react to the industries in providing low actuation voltage MEMS capacitive switches with low loss and high isolation and make it possible to be integrated with CMOS circuit. MEMS capacitive switches with three different support structure namely fixed-fixed beam, single meander and double meander have been designed and simulated in both standard and proposed structure. A standard switch consists of two parallel electrodes and a proposed switch consists of three parallel electrodes. Designing using schematic capture begin by selecting the suitable component from electromechanical library to represent membrane, support structure, anchor, bottom electrode, top electrode, ground, transmission line-in and transmission line-out. The schematic diagram has been simulated and translated to 2D layout and 3D model for physical verification. The electromechanical analysis has been carried out using DC Transfer Analysis. In DC Transfer Analysis, the value of pull-in voltage, up-state and down-state capacitance can be attained. In Small Signal Frequency Analysis the value of resonant frequency is obtained. The measurement of RF performance was done using RF Electrical Analysis. Simulation result shows the pull-in voltage for all proposed design has been reduced 40%-50% as compared to their standard counterpart. While the result for other performance including capacitances for three electrodes switch has almost same value as two electrodes structure. The switch indicates low insertion loss (&lt;-0.4db) in the up-state position and high isolation (&gt;-26dB) in the down-state position. This concludes that the additional top membrane does maintain the good electromechanical and RF performance of MEMS capacitive switch