Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm

A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the combination of behavioral models for performance evaluation, optimization routines to minimize the power and area consumption of the circuit solution, and an algorithm to efficiently constraint the converter design space. This algorithm precludes the cost of lengthy bottom-up verifications and speeds up the synthesis task. The approach is herein demonstrated via the design of a 0.13 μm CMOS 10 bits@60 MS/s pipeline ADC with energy consumption per conversion of only 0.54 pJ@1 MHz, making it one of the most energy-efficient 10-bit video-rate pipeline ADCs reported to date. The computational cost of this design is of only 25 min of CPU time, and includes the evaluation of 13 different pipeline architectures potentially feasible for the targeted specifications. The optimum design derived from the synthesis procedure has been fine tuned to support PVT variations, laid out together with other auxiliary blocks, and fabricated. The experimental results show a power consumption of 23 [email protected] V and an effective resolution of 9.47-bit@1 MHz. Bearing in mind that no specific power reduction strategy has been applied; the mentioned results confirm the reliability of the proposed approach.Ministerio de Ciencia e Innovación TEC2009-08447Junta de Andalucía TIC-0281

Advanced Algorithms for Satellite Communication Signal Processing

Dizertační práce je zaměřena na softwarově definované přijímače určené k úzkopásmové družicové komunikaci. Komunikační kanály družicových spojů zahrnujících komunikaci s hlubokým vesmírem jsou zatíženy vysokými úrovněmi šumu, typicky modelovaného AWGN, a silným Dopplerovým posuvem signálu způsobeným mimořádnou rychlostí pohybu objektu. Dizertační práce představuje možné postupy řešení výpočetně efektivní digitální downkonverze úzkopásmových signálů a systému odhadu kmitočtu nosné úzkopásmových signálů zatížených Dopplerovým posuvem v řádu násobků šířky pásma signálu. Popis navrhovaných algoritmů zahrnuje analytický postup jejich vývoje a tam, kde je to možné, i analytické hodnocení jejich chování. Algoritmy jsou modelovány v prostředí MATLAB Simulink a tyto modely jsou využity pro ověření vlastností simulacemi. Modely byly také využity k experimentálním testům na reálném signálu přijatém z družice PSAT v laboratoři experimentálních družic na ústavu radioelektroniky.The dissertation is focused on software defined receivers intended for narrowband satellite communication. The satellite communication channel including deep space communication suffers from a high level of noise, typically modeled by AWGN, and from a strong Doppler shift of a signal caused by the unprecedented speed of an object in motion. The dissertation shows possible approaches to the issues of computationally efficient digital downconversion of narrowband signals and the carrier frequency estimation of narrowband signals distorted by the Doppler shift in the order of multiples of the signal bandwidth. The description of the proposed algorithms includes an analytical approach of its development and, if possible, the analytical performance assessment. The algorithms are modeled in MATLAB Simulink and the models are used for validating the performance by the simulation. The models were also used for experimental tests on the real signal received from the PSAT satellite at the laboratory of experimental satellites at the department of radio electronics.

On Low-Resolution ADCs in Practical 5G Millimeter-Wave Massive MIMO Systems

Nowadays, millimeter-wave (mmWave) massive multiple-input multiple-output (MIMO) systems is a favorable candidate for the fifth generation (5G) cellular systems. However, a key challenge is the high power consumption imposed by its numerous radio frequency (RF) chains, which may be mitigated by opting for low-resolution analog-to-digital converters (ADCs), whilst tolerating a moderate performance loss. In this article, we discuss several important issues based on the most recent research on mmWave massive MIMO systems relying on low-resolution ADCs. We discuss the key transceiver design challenges including channel estimation, signal detector, channel information feedback and transmit precoding. Furthermore, we introduce a mixed-ADC architecture as an alternative technique of improving the overall system performance. Finally, the associated challenges and potential implementations of the practical 5G mmWave massive MIMO system {with ADC quantizers} are discussed.Comment: to appear in IEEE Communications Magazin

Developing Model-Based Design Evaluation for Pipelined A/D Converters

This paper deals with a prospective approach of modeling, design evaluation and error determination applied to pipelined A/D converter architecture. In contrast with conventional ADC modeling algorithms targeted to extract the maximum ADC non-linearity error, the innovative approach presented allows to decompose magnitudes of individual error sources from a measured or simulated response of an ADC device. Design Evaluation methodology was successfully applied to Nyquist rate cyclic converters in our works [13]. Now, we extend its principles to pipelined architecture. This qualitative decomposition can significantly contribute to the ADC calibration procedure performed on the production line in term of integral and differential nonlinearity. This is backgrounded by the fact that the knowledge of ADC performance contributors provided by the proposed method helps to adjust the values of on-chip converter components so as to equalize (and possibly minimize) the total non-linearity error. In this paper, the design evaluation procedure is demonstrated on a system design example of pipelined A/D converter. Significant simulation results of each stage of the design evaluation process are given, starting from the INL performance extraction proceeded in a powerful Virtual Testing Environment implemented in Maple™ software and finishing by an error source simulation, modeling of pipelined ADC structure and determination of error source contribution, suitable for a generic process flow

On-chip evaluation of oscillation-based-test output signals for switched-capacitor circuits

This work presents a simple and low-cost method for on-chip evaluation of test signals coming from the application of the Oscillation-Based-Test (OBT) technique. This method extracts the main test signal features (amplitude, frequency and DC level) in the digital domain requiring just a very simple and robust circuitry. Experimental results obtained from an integrated chip demonstrate the feasibility of the approac

Comparative Analysis among DSP and FPGA-based Control Capabilities in PWM Power Converters

PWM power converters are close to be mature for standard diffusion. New FPGA technologies could now realise at best the digital control key-points: flexible performance and time to market. The paper deals with the new digital control properties of FPGA-based techniques. On the basis of reference structures, a comparative analysis is carried-out trading-off dynamic performances and immunity to PWM environment. All possible sampled control or DSP techniques are firstly analysed and compared to each other. A breakthrough concept for FPGAs is defined, definitely solving for PWM feedback immunity by practical over-sampling and parallel processing while improving dynamic performances. Simulation tests and the application of dead-beat control clearly point-out the respective dynamic properties

DIGITALLY ASSISTED TECHNIQUES FOR NYQUIST RATE ANALOG-to-DIGITAL CONVERTERS

With the advance of technology and rapid growth of digital systems, low power high speed analog-to-digital converters with great accuracy are in demand. To achieve high effective number of bits Analog-to-Digital Converter(ADC) calibration as a time consuming process is a potential bottleneck for designs. This dissertation presentsa fully digital background calibration algorithm for a 7-bit redundant flash ADC using split structure and look-up table based correction. Redundant comparators are used in the flash ADC design of this work in order to tolerate large offset voltages while minimizing signal input capacitance. The split ADC structure helps by eliminating the unknown input signal from the calibration path. The flash ADC has been designed in 180nm IBM CMOS technology and fabricated through MOSIS. This work was supported by Analog Devices, Wilmington,MA. While much research on ADC design has concentrated on increasing resolution and sample rate, there are many applications (e.g. biomedical devices and sensor networks) that do not require high performance but do require low power energy efficient ADCs. This dissertation also explores on design of a low quiescent current 100kSps Successive Approximation (SAR) ADC that has been used as an error detection ADC for an automotive application in 350nm CD (CMOS-DMOS) technology. This work was supported by ON Semiconductor Corp, East Greenwich,RI

CMOS design of a current-mode multiplier/divider circuit with applications to fuzzy controllers

Multiplier and divider circuits are usually required in the fields of analog signal processing and parallel-computing neural or fuzzy systems. In particular, this paper focuses on the hardware implementation of fuzzy controllers, where the divider circuit is usually the bottleneck. Multiplier/divider circuits can be implemented with a combination of A/D-D/A converters. An efficient design based on current-mode data converters is presented herein. Continuous-time algorithmic converters are chosen to reduce the control circuitry and to obtain a modular design based on a cascade of bit cells. Several circuit structures to implement these cells are presented and discussed. The one that is selected enables a better trade-off speed/power than others previously reported in the literature while maintaining a low area occupation. The resulting multiplier/divider circuit offers a low voltage operation, provides the division result in both analog and digital formats, and it is suitable for applications of low or middle resolution (up to 9 bits) like applications to fuzzy controllers. The analysis is illustrated with Hspice simulations and experimental results from a CMOS multiplier/divider prototype with 5-bit resolution. Experimental results from a CMOS current-mode fuzzy controller chip that contains the proposed design are also included