136 research outputs found

    Deliverable D4.1: VLC modulation schemes

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    This report presents the analysis of different modulation schemes D4.1 for VLC systems of the VIDAS project. Considering the final prototype design and application, the deliverable D4.1 was projected. The detail analysis of various modulation schemes are carried out and a robust technique based on direct sequence spread spectrum (DSSS) is followed. DSSS technique though necessitates use of high bandwidth while minimizing the effect of noise. Since the final application does not require very high dat a rate of transmission but robustness against the noise (external lights) becomes necessary. The analysis is followed by model development using Matlab/Simulink. The performance of both of these systems are compared and evaluated. Some of the simulation results are presented

    Displays, memories, and signal processing: A compilation

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    Articles on electronics systems and techniques were presented. The first section is on displays and other electro-optical systems; the second section is devoted to signal processing. The third section presented several new memory devices for digital equipment, including articles on holographic memories. The latest patent information available is also given

    Implementation of a coded-reference ultra-wideband system

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    Ankara : The Department of Electrical and Electronics Engineering and the Institute of Engineering and Sciences of Bilkent University, 2011.Thesis (Master's) -- Bilkent University, 2011.Includes bibliographical references leaves 60-64.Coded-reference ultra-wideband (CR UWB) systems provide orthogonalization of the reference and data signals in the code domain to facilitate communications without the need for complex channel estimation and have significant advantages over the previous techniques in terms of performance and/or implementation complexity. This thesis presents a UWB testbed as a general experimental platform to explore pulse-based UWB communications and discusses design and implementation issues. A testbed is built as a flexible solution for hardware implementation of a CR UWB system.Gรผrlevik, OsmanM.S

    Analog Baseband Filters and Mixed Signal Circuits for Broadband Receiver Systems

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    Data transfer rates of communication systems continue to rise fueled by aggressive demand for voice, video and Internet data. Device scaling enabled by modern lithography has paved way for System-on-Chip solutions integrating compute intensive digital signal processing. This trend coupled with demand for low power, battery-operated consumer devices offers extensive research opportunities in analog and mixed-signal designs that enable modern communication systems. The first part of the research deals with broadband wireless receivers. With an objective to gain insight, we quantify the impact of undesired out-band blockers on analog baseband in a broadband radio. We present a systematic evaluation of the dynamic range requirements at the baseband and A/D conversion boundary. A prototype UHF receiver designed using RFCMOS 0.18[mu]m technology to support this research integrates a hybrid continuous- and discrete-time analog baseband along with the RF front-end. The chip consumes 120mW from a 1.8V/2.5V dual supply and achieves a noise figure of 7.9dB, an IIP3 of -8dBm (+2dbm) at maximum gain (at 9dB RF attenuation). High linearity active RC filters are indispensable in wireless radios. A novel feed-forward OTA applicable to active RC filters in analog baseband is presented. Simulation results from the chip prototype designed in RFCMOS 0.18[mu]m technology show an improvement in the out-band linearity performance that translates to increased dynamic range in the presence of strong adjacent blockers. The second part of the research presents an adaptive clock-recovery system suitable for high-speed wireline transceivers. The main objective is to improve the jitter-tracking and jitter-filtering trade-off in serial link clock-recovery applications. A digital state-machine that enables the proposed mixed-signal adaptation solution to achieve this objective is presented. The advantages of the proposed mixed-signal solution operating at 10Gb/s are supported by experimental results from the prototype in RFCMOS 0.18[mu]m technology

    Application of advanced on-board processing concepts to future satellite communications systems

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    An initial definition of on-board processing requirements for an advanced satellite communications system to service domestic markets in the 1990's is presented. An exemplar system architecture with both RF on-board switching and demodulation/remodulation baseband processing was used to identify important issues related to system implementation, cost, and technology development

    RAPID CLOCK RECOVERY ALGORITHMS FOR DIGITAL MAGNETIC RECORDING AND DATA COMMUNICATIONS

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    SIGLEAvailable from British Library Document Supply Centre-DSC:DXN024293 / BLDSC - British Library Document Supply CentreGBUnited Kingdo

    ๊ณ ์† ์‹œ๋ฆฌ์–ผ ๋งํฌ๋ฅผ ์œ„ํ•œ ๊ณ ๋ฆฌ ๋ฐœ์ง„๊ธฐ๋ฅผ ๊ธฐ๋ฐ˜์œผ๋กœ ํ•˜๋Š” ์ฃผํŒŒ์ˆ˜ ํ•ฉ์„ฑ๊ธฐ

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    ํ•™์œ„๋…ผ๋ฌธ(๋ฐ•์‚ฌ) -- ์„œ์šธ๋Œ€ํ•™๊ต๋Œ€ํ•™์› : ๊ณต๊ณผ๋Œ€ํ•™ ์ „๊ธฐยท์ •๋ณด๊ณตํ•™๋ถ€, 2022. 8. ์ •๋•๊ท .In this dissertation, major concerns in the clocking of modern serial links are discussed. As sub-rate, multi-standard architectures are becoming predominant, the conventional clocking methodology seems to necessitate innovation in terms of low-cost implementation. Frequency synthesis with active, inductor-less oscillators replacing LC counterparts are reviewed, and solutions for two major drawbacks are proposed. Each solution is verified by prototype chip design, giving a possibility that the inductor-less oscillator may become a proper candidate for future high-speed serial links. To mitigate the high flicker noise of a high-frequency ring oscillator (RO), a reference multiplication technique that effectively extends the bandwidth of the following all-digital phase-locked loop (ADPLL) is proposed. The technique avoids any jitter accumulation, generating a clean mid-frequency clock, overall achieving high jitter performance in conjunction with the ADPLL. Timing constraint for the proper reference multiplication is first analyzed to determine the calibration points that may correct the existent phase errors. The weight for each calibration point is updated by the proposed a priori probability-based least-mean-square (LMS) algorithm. To minimize the time required for the calibration, each gain for the weight update is adaptively varied by deducing a posteriori which error source dominates the others. The prototype chip is fabricated in a 40-nm CMOS technology, and its measurement results verify the low-jitter, high-frequency clock generation with fast calibration settling. The presented work achieves an rms jitter of 177/223 fs at 8/16-GHz output, consuming 12.1/17-mW power. As the second embodiment, an RO-based ADPLL with an analog technique that addresses the high supply sensitivity of the RO is presented. Unlike prior arts, the circuit for the proposed technique does not extort the RO voltage headroom, allowing high-frequency oscillation. Further, the performance given from the technique is robust over process, voltage, and temperature (PVT) variations, avoiding the use of additional calibration hardware. Lastly, a comprehensive analysis of phase noise contribution is conducted for the overall ADPLL, followed by circuit optimizations, to retain the low-jitter output. Implemented in a 40-nm CMOS technology, the frequency synthesizer achieves an rms jitter of 289 fs at 8 GHz output without any injected supply noise. Under a 20-mVrms white supply noise, the ADPLL suppresses supply-noise-induced jitter by -23.8 dB.๋ณธ ๋…ผ๋ฌธ์€ ํ˜„๋Œ€ ์‹œ๋ฆฌ์–ผ ๋งํฌ์˜ ํด๋ฝํ‚น์— ๊ด€์—ฌ๋˜๋Š” ์ฃผ์š”ํ•œ ๋ฌธ์ œ๋“ค์— ๋Œ€ํ•˜์—ฌ ๊ธฐ์ˆ ํ•œ๋‹ค. ์ค€์†๋„, ๋‹ค์ค‘ ํ‘œ์ค€ ๊ตฌ์กฐ๋“ค์ด ์ฑ„ํƒ๋˜๊ณ  ์žˆ๋Š” ์ถ”์„ธ์— ๋”ฐ๋ผ, ๊ธฐ์กด์˜ ํด๋ผํ‚น ๋ฐฉ๋ฒ•์€ ๋‚ฎ์€ ๋น„์šฉ์˜ ๊ตฌํ˜„์˜ ๊ด€์ ์—์„œ ์ƒˆ๋กœ์šด ํ˜์‹ ์„ ํ•„์š”๋กœ ํ•œ๋‹ค. LC ๊ณต์ง„๊ธฐ๋ฅผ ๋Œ€์‹ ํ•˜์—ฌ ๋Šฅ๋™ ์†Œ์ž ๋ฐœ์ง„๊ธฐ๋ฅผ ์‚ฌ์šฉํ•œ ์ฃผํŒŒ์ˆ˜ ํ•ฉ์„ฑ์— ๋Œ€ํ•˜์—ฌ ์•Œ์•„๋ณด๊ณ , ์ด์— ๋ฐœ์ƒํ•˜๋Š” ๋‘๊ฐ€์ง€ ์ฃผ์š” ๋ฌธ์ œ์ ๊ณผ ๊ฐ๊ฐ์— ๋Œ€ํ•œ ํ•ด๊ฒฐ ๋ฐฉ์•ˆ์„ ํƒ์ƒ‰ํ•œ๋‹ค. ๊ฐ ์ œ์•ˆ ๋ฐฉ๋ฒ•์„ ํ”„๋กœํ† ํƒ€์ž… ์นฉ์„ ํ†ตํ•ด ๊ทธ ํšจ์šฉ์„ฑ์„ ๊ฒ€์ฆํ•˜๊ณ , ์ด์–ด์„œ ๋Šฅ๋™ ์†Œ์ž ๋ฐœ์ง„๊ธฐ๊ฐ€ ๋ฏธ๋ž˜์˜ ๊ณ ์† ์‹œ๋ฆฌ์–ผ ๋งํฌ์˜ ํด๋ฝํ‚น์— ์‚ฌ์šฉ๋  ๊ฐ€๋Šฅ์„ฑ์— ๋Œ€ํ•ด ๊ฒ€ํ† ํ•œ๋‹ค. ์ฒซ๋ฒˆ์งธ ์‹œ์—ฐ์œผ๋กœ์จ, ๊ณ ์ฃผํŒŒ ๊ณ ๋ฆฌ ๋ฐœ์ง„๊ธฐ์˜ ๋†’์€ ํ”Œ๋ฆฌ์ปค ์žก์Œ์„ ์™„ํ™”์‹œํ‚ค๊ธฐ ์œ„ํ•ด ๊ธฐ์ค€ ์‹ ํ˜ธ๋ฅผ ๋ฐฐ์ˆ˜ํ™”ํ•˜์—ฌ ๋’ท๋‹จ์˜ ์œ„์ƒ ๊ณ ์ • ๋ฃจํ”„์˜ ๋Œ€์—ญํญ์„ ํšจ๊ณผ์ ์œผ๋กœ ๊ทน๋Œ€ํ™” ์‹œํ‚ค๋Š” ํšŒ๋กœ ๊ธฐ์ˆ ์„ ์ œ์•ˆํ•œ๋‹ค. ๋ณธ ๊ธฐ์ˆ ์€ ์ง€ํ„ฐ๋ฅผ ๋ˆ„์  ์‹œํ‚ค์ง€ ์•Š์œผ๋ฉฐ ๋”ฐ๋ผ์„œ ๊นจ๋—ํ•œ ์ค‘๊ฐ„ ์ฃผํŒŒ์ˆ˜ ํด๋ฝ์„ ์ƒ์„ฑ์‹œ์ผœ ์œ„์ƒ ๊ณ ์ • ๋ฃจํ”„์™€ ํ•จ๊ป˜ ๋†’์€ ์„ฑ๋Šฅ์˜ ๊ณ ์ฃผํŒŒ ํด๋ฝ์„ ํ•ฉ์„ฑํ•œ๋‹ค. ๊ธฐ์ค€ ์‹ ํ˜ธ๋ฅผ ์„ฑ๊ณต์ ์œผ๋กœ ๋ฐฐ์ˆ˜ํ™”ํ•˜๊ธฐ ์œ„ํ•œ ํƒ€์ด๋ฐ ์กฐ๊ฑด๋“ค์„ ๋จผ์ € ๋ถ„์„ํ•˜์—ฌ ํƒ€์ด๋ฐ ์˜ค๋ฅ˜๋ฅผ ์ œ๊ฑฐํ•˜๊ธฐ ์œ„ํ•œ ๋ฐฉ๋ฒ•๋ก ์„ ํŒŒ์•…ํ•œ๋‹ค. ๊ฐ ๊ต์ • ์ค‘๋Ÿ‰์€ ์—ฐ์—ญ์  ํ™•๋ฅ ์„ ๊ธฐ๋ฐ˜์œผ๋กœํ•œ LMS ์•Œ๊ณ ๋ฆฌ์ฆ˜์„ ํ†ตํ•ด ๊ฐฑ์‹ ๋˜๋„๋ก ์„ค๊ณ„๋œ๋‹ค. ๊ต์ •์— ํ•„์š”ํ•œ ์‹œ๊ฐ„์„ ์ตœ์†Œํ™” ํ•˜๊ธฐ ์œ„ํ•˜์—ฌ, ๊ฐ ๊ต์ • ์ด๋“์€ ํƒ€์ด๋ฐ ์˜ค๋ฅ˜ ๊ทผ์›๋“ค์˜ ํฌ๊ธฐ๋ฅผ ๊ท€๋‚ฉ์ ์œผ๋กœ ์ถ”๋ก ํ•œ ๊ฐ’์„ ๋ฐ”ํƒ•์œผ๋กœ ์ง€์†์ ์œผ๋กœ ์ œ์–ด๋œ๋‹ค. 40-nm CMOS ๊ณต์ •์œผ๋กœ ๊ตฌํ˜„๋œ ํ”„๋กœํ† ํƒ€์ž… ์นฉ์˜ ์ธก์ •์„ ํ†ตํ•ด ์ €์†Œ์Œ, ๊ณ ์ฃผํŒŒ ํด๋ฝ์„ ๋น ๋ฅธ ๊ต์ • ์‹œ๊ฐ„์•ˆ์— ํ•ฉ์„ฑํ•ด ๋ƒ„์„ ํ™•์ธํ•˜์˜€๋‹ค. ์ด๋Š” 177/223 fs์˜ rms ์ง€ํ„ฐ๋ฅผ ๊ฐ€์ง€๋Š” 8/16 GHz์˜ ํด๋ฝ์„ ์ถœ๋ ฅํ•œ๋‹ค. ๋‘๋ฒˆ์งธ ์‹œ์—ฐ์œผ๋กœ์จ, ๊ณ ๋ฆฌ ๋ฐœ์ง„๊ธฐ์˜ ๋†’์€ ์ „์› ๋…ธ์ด์ฆˆ ์˜์กด์„ฑ์„ ์™„ํ™”์‹œํ‚ค๋Š” ๊ธฐ์ˆ ์ด ํฌํ•จ๋œ ์ฃผํŒŒ์ˆ˜ ํ•ฉ์„ฑ๊ธฐ๊ฐ€ ์„ค๊ณ„๋˜์—ˆ๋‹ค. ์ด๋Š” ๊ณ ๋ฆฌ ๋ฐœ์ง„๊ธฐ์˜ ์ „์•• ํ—ค๋“œ๋ฃธ์„ ๋ณด์กดํ•จ์œผ๋กœ์„œ ๊ณ ์ฃผํŒŒ ๋ฐœ์ง„์„ ๊ฐ€๋Šฅํ•˜๊ฒŒ ํ•œ๋‹ค. ๋‚˜์•„๊ฐ€, ์ „์› ๋…ธ์ด์ฆˆ ๊ฐ์†Œ ์„ฑ๋Šฅ์€ ๊ณต์ •, ์ „์••, ์˜จ๋„ ๋ณ€๋™์— ๋Œ€ํ•˜์—ฌ ๋ฏผ๊ฐํ•˜์ง€ ์•Š์œผ๋ฉฐ, ๋”ฐ๋ผ์„œ ์ถ”๊ฐ€์ ์ธ ๊ต์ • ํšŒ๋กœ๋ฅผ ํ•„์š”๋กœ ํ•˜์ง€ ์•Š๋Š”๋‹ค. ๋งˆ์ง€๋ง‰์œผ๋กœ, ์œ„์ƒ ๋…ธ์ด์ฆˆ์— ๋Œ€ํ•œ ํฌ๊ด„์  ๋ถ„์„๊ณผ ํšŒ๋กœ ์ตœ์ ํ™”๋ฅผ ํ†ตํ•˜์—ฌ ์ฃผํŒŒ์ˆ˜ ํ•ฉ์„ฑ๊ธฐ์˜ ์ €์žก์Œ ์ถœ๋ ฅ์„ ๋ฐฉํ•ดํ•˜์ง€ ์•Š๋Š” ๋ฐฉ๋ฒ•์„ ๊ณ ์•ˆํ•˜์˜€๋‹ค. ํ•ด๋‹น ํ”„๋กœํ† ํƒ€์ž… ์นฉ์€ 40-nm CMOS ๊ณต์ •์œผ๋กœ ๊ตฌํ˜„๋˜์—ˆ์œผ๋ฉฐ, ์ „์› ๋…ธ์ด์ฆˆ๊ฐ€ ์ธ๊ฐ€๋˜์ง€ ์•Š์€ ์ƒํƒœ์—์„œ 289 fs์˜ rms ์ง€ํ„ฐ๋ฅผ ๊ฐ€์ง€๋Š” 8 GHz์˜ ํด๋ฝ์„ ์ถœ๋ ฅํ•œ๋‹ค. ๋˜ํ•œ, 20 mVrms์˜ ์ „์› ๋…ธ์ด์ฆˆ๊ฐ€ ์ธ๊ฐ€๋˜์—ˆ์„ ๋•Œ์— ์œ ๋„๋˜๋Š” ์ง€ํ„ฐ์˜ ์–‘์„ -23.8 dB ๋งŒํผ ์ค„์ด๋Š” ๊ฒƒ์„ ํ™•์ธํ•˜์˜€๋‹ค.1 Introduction 1 1.1 Motivation 3 1.1.1 Clocking in High-Speed Serial Links 4 1.1.2 Multi-Phase, High-Frequency Clock Conversion 8 1.2 Dissertation Objectives 10 2 RO-Based High-Frequency Synthesis 12 2.1 Phase-Locked Loop Fundamentals 12 2.2 Toward All-Digital Regime 15 2.3 RO Design Challenges 21 2.3.1 Oscillator Phase Noise 21 2.3.2 Challenge 1: High Flicker Noise 23 2.3.3 Challenge 2: High Supply Noise Sensitivity 26 3 Filtering RO Noise 28 3.1 Introduction 28 3.2 Proposed Reference Octupler 34 3.2.1 Delay Constraint 34 3.2.2 Phase Error Calibration 38 3.2.3 Circuit Implementation 51 3.3 IL-ADPLL Implementation 55 3.4 Measurement Results 59 3.5 Summary 63 4 RO Supply Noise Compensation 69 4.1 Introduction 69 4.2 Proposed Analog Closed Loop for Supply Noise Compensation 72 4.2.1 Circuit Implementation 73 4.2.2 Frequency-Domain Analysis 76 4.2.3 Circuit Optimization 81 4.3 ADPLL Implementation 87 4.4 Measurement Results 90 4.5 Summary 98 5 Conclusions 99 A Notes on the 8REF 102 B Notes on the ACSC 105๋ฐ•

    Engineering evaluations and studies. Volume 3: Exhibit C

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    High rate multiplexes asymmetry and jitter, data-dependent amplitude variations, and transition density are discussed
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