136 research outputs found
Deliverable D4.1: VLC modulation schemes
This report presents the
analysis of different modulation schemes D4.1 for VLC systems
of
the VIDAS project.
Considering the final
prototype design and
application, the
deliverable D4.1 was projected.
The
detail analysis of various modulation schemes are carried out and a robust technique
based on direct sequence spread spectrum (DSSS) is followed. DSSS technique though
necessitates use of high bandwidth while minimizing the effect of noise. Since the final
application does not require very high dat
a rate of transmission but robustness against the
noise (external lights)
becomes necessary. The analysis is followed by model development
using Matlab/Simulink.
The performance of both of these systems are compared and
evaluated.
Some of the simulation
results are presented
Displays, memories, and signal processing: A compilation
Articles on electronics systems and techniques were presented. The first section is on displays and other electro-optical systems; the second section is devoted to signal processing. The third section presented several new memory devices for digital equipment, including articles on holographic memories. The latest patent information available is also given
Recommended from our members
Multiservice Ethernet Digital Distributed Antenna Systems
Over 90% of wireless communications traffic occurs indoors and in-building wireless coverage is still one of the biggest obstacles for wireless users. As the growing demands on wireless capacity, coverage and connectivity have led to 4G and 5G standards, it has also become increasingly important to design and implement future-proof indoor wireless services in a cost effective manner. This thesis introduces a novel multi-service digital distributed antenna systems (DDAS) for indoor wireless coverage, which not only is able to transport multiple wireless carriers from different vendors and mobile operators, but also allows a converged architecture to integrate indoor wireless system with existing Ethernet infrastructures. The Cloud Radio Access Networks (C-RAN) has been suggested by major telecom vendors as the main architecture for last-mile coverage in 5G. However, the digital fronthaul interface defined in common public radio interface (CPRI), which is most widely adopted standard for C-RAN, requires very expensive infrastructures to be built due to the high data rate generated after digitisation. A solution has been introduced at the University of Cambridge previously to remove the digital redundancy by using a data compression technique which has shown 3-times higher transmission efficiency than CPRI. This thesis extends the concept to a more robust architecture allowing multiple wireless services to be transmitted simultaneously as well as being carried over standard Ethernet without losing the Quality of End-user Experience (QoE) and the Quality of Service (QoS) of in-building mobile network.
A two-channel DDAS system with data compression algorithm is experimentally demonstrated, showing wide RF dynamic range for both 4G LTE service and 3G WCDMA service simultaneously carried over a single fibre-based infrastructure. The system leads to the design and implementation of full-service DDAS system allowing 14 channels (all 2/3/4G service from three major mobile operators) to be carried over single 10Gbps network. Typically, the system using CPRI will need over 30Gbps network to be installed for wireless coverage.
Another key aspect covered in this thesis is the design and implementation of the multi-service DDAS over Ethernet (Eth-DDAS). Due to the stringent latency requirement in wireless services, mitigation of delays and errors in frame ordering has become a key challenge for putting DDAS over Ethernet. To overcome these problems, a special Eth-DDAS frame structure is proposed in this thesis. After digitisation, digital signal bearing RF information is packetised onto Ethernet-compatible frames with additional timestamps and sequence numbers before transported via fibre to the receiver. Three latency scenarios are tested with different payload sizes of the proposed frame structure and real-time RF performance is measured to prove the capability of implementation of such system in real-life using commercial off-the-shelf (COTS) ADC/DAC and FPGAs
Implementation of a coded-reference ultra-wideband system
Ankara : The Department of Electrical and Electronics Engineering and the Institute of Engineering and Sciences of Bilkent University, 2011.Thesis (Master's) -- Bilkent University, 2011.Includes bibliographical references leaves 60-64.Coded-reference ultra-wideband (CR UWB) systems provide orthogonalization
of the reference and data signals in the code domain to facilitate communications
without the need for complex channel estimation and have significant
advantages over the previous techniques in terms of performance and/or implementation
complexity. This thesis presents a UWB testbed as a general experimental
platform to explore pulse-based UWB communications and discusses
design and implementation issues. A testbed is built as a flexible solution for
hardware implementation of a CR UWB system.Gรผrlevik, OsmanM.S
Analog Baseband Filters and Mixed Signal Circuits for Broadband Receiver Systems
Data transfer rates of communication systems continue to rise fueled by aggressive demand for voice, video and Internet data. Device scaling enabled by modern lithography has paved way for System-on-Chip solutions integrating compute intensive digital signal processing. This trend coupled with demand for low power, battery-operated consumer devices offers extensive research opportunities in analog and mixed-signal designs that enable modern communication systems.
The first part of the research deals with broadband wireless receivers. With an objective to gain insight, we quantify the impact of undesired out-band blockers on analog baseband in a broadband radio. We present a systematic evaluation of the dynamic range requirements at the baseband and A/D conversion boundary. A prototype UHF receiver designed using RFCMOS 0.18[mu]m technology to support this research integrates a hybrid continuous- and discrete-time analog baseband along with the RF front-end. The chip consumes 120mW from a 1.8V/2.5V dual supply and achieves a noise figure of 7.9dB, an IIP3 of -8dBm (+2dbm) at maximum gain (at 9dB RF attenuation).
High linearity active RC filters are indispensable in wireless radios. A novel feed-forward OTA applicable to active RC filters in analog baseband is presented.
Simulation results from the chip prototype designed in RFCMOS 0.18[mu]m technology show an improvement in the out-band linearity performance that translates to increased dynamic range in the presence of strong adjacent blockers.
The second part of the research presents an adaptive clock-recovery system suitable for high-speed wireline transceivers. The main objective is to improve the jitter-tracking and jitter-filtering trade-off in serial link clock-recovery applications. A digital state-machine that enables the proposed mixed-signal adaptation solution to achieve this objective is presented. The advantages of the proposed mixed-signal solution operating at 10Gb/s are supported by experimental results from the prototype in RFCMOS 0.18[mu]m technology
Application of advanced on-board processing concepts to future satellite communications systems
An initial definition of on-board processing requirements for an advanced satellite communications system to service domestic markets in the 1990's is presented. An exemplar system architecture with both RF on-board switching and demodulation/remodulation baseband processing was used to identify important issues related to system implementation, cost, and technology development
RAPID CLOCK RECOVERY ALGORITHMS FOR DIGITAL MAGNETIC RECORDING AND DATA COMMUNICATIONS
SIGLEAvailable from British Library Document Supply Centre-DSC:DXN024293 / BLDSC - British Library Document Supply CentreGBUnited Kingdo
๊ณ ์ ์๋ฆฌ์ผ ๋งํฌ๋ฅผ ์ํ ๊ณ ๋ฆฌ ๋ฐ์ง๊ธฐ๋ฅผ ๊ธฐ๋ฐ์ผ๋ก ํ๋ ์ฃผํ์ ํฉ์ฑ๊ธฐ
ํ์๋
ผ๋ฌธ(๋ฐ์ฌ) -- ์์ธ๋ํ๊ต๋ํ์ : ๊ณต๊ณผ๋ํ ์ ๊ธฐยท์ ๋ณด๊ณตํ๋ถ, 2022. 8. ์ ๋๊ท .In this dissertation, major concerns in the clocking of modern serial links are discussed. As sub-rate, multi-standard architectures are becoming predominant, the conventional clocking methodology seems to necessitate innovation in terms of low-cost implementation. Frequency synthesis with active, inductor-less oscillators replacing LC counterparts are reviewed, and solutions for two major drawbacks are proposed. Each solution is verified by prototype chip design, giving a possibility that the inductor-less oscillator may become a proper candidate for future high-speed serial links.
To mitigate the high flicker noise of a high-frequency ring oscillator (RO), a reference multiplication technique that effectively extends the bandwidth of the following all-digital phase-locked loop (ADPLL) is proposed. The technique avoids any jitter accumulation, generating a clean mid-frequency clock, overall achieving high jitter performance in conjunction with the ADPLL. Timing constraint for the proper reference multiplication is first analyzed to determine the calibration points that may correct the existent phase errors. The weight for each calibration point is updated by the proposed a priori probability-based least-mean-square (LMS) algorithm. To minimize the time required for the calibration, each gain for the weight update is adaptively varied by deducing a posteriori which error source dominates the others. The prototype chip is fabricated in a 40-nm CMOS technology, and its measurement results verify the low-jitter, high-frequency clock generation with fast calibration settling. The presented work achieves an rms jitter of 177/223 fs at 8/16-GHz output, consuming 12.1/17-mW power.
As the second embodiment, an RO-based ADPLL with an analog technique that addresses the high supply sensitivity of the RO is presented. Unlike prior arts, the circuit for the proposed technique does not extort the RO voltage headroom, allowing high-frequency oscillation. Further, the performance given from the technique is robust over process, voltage, and temperature (PVT) variations, avoiding the use of additional calibration hardware. Lastly, a comprehensive analysis of phase noise contribution is conducted for the overall ADPLL, followed by circuit optimizations, to retain the low-jitter output. Implemented in a 40-nm CMOS technology, the frequency synthesizer achieves an rms jitter of 289 fs at 8 GHz output without any injected supply noise. Under a 20-mVrms white supply noise, the ADPLL suppresses supply-noise-induced jitter by -23.8 dB.๋ณธ ๋
ผ๋ฌธ์ ํ๋ ์๋ฆฌ์ผ ๋งํฌ์ ํด๋ฝํน์ ๊ด์ฌ๋๋ ์ฃผ์ํ ๋ฌธ์ ๋ค์ ๋ํ์ฌ ๊ธฐ์ ํ๋ค. ์ค์๋, ๋ค์ค ํ์ค ๊ตฌ์กฐ๋ค์ด ์ฑํ๋๊ณ ์๋ ์ถ์ธ์ ๋ฐ๋ผ, ๊ธฐ์กด์ ํด๋ผํน ๋ฐฉ๋ฒ์ ๋ฎ์ ๋น์ฉ์ ๊ตฌํ์ ๊ด์ ์์ ์๋ก์ด ํ์ ์ ํ์๋ก ํ๋ค. LC ๊ณต์ง๊ธฐ๋ฅผ ๋์ ํ์ฌ ๋ฅ๋ ์์ ๋ฐ์ง๊ธฐ๋ฅผ ์ฌ์ฉํ ์ฃผํ์ ํฉ์ฑ์ ๋ํ์ฌ ์์๋ณด๊ณ , ์ด์ ๋ฐ์ํ๋ ๋๊ฐ์ง ์ฃผ์ ๋ฌธ์ ์ ๊ณผ ๊ฐ๊ฐ์ ๋ํ ํด๊ฒฐ ๋ฐฉ์์ ํ์ํ๋ค. ๊ฐ ์ ์ ๋ฐฉ๋ฒ์ ํ๋กํ ํ์
์นฉ์ ํตํด ๊ทธ ํจ์ฉ์ฑ์ ๊ฒ์ฆํ๊ณ , ์ด์ด์ ๋ฅ๋ ์์ ๋ฐ์ง๊ธฐ๊ฐ ๋ฏธ๋์ ๊ณ ์ ์๋ฆฌ์ผ ๋งํฌ์ ํด๋ฝํน์ ์ฌ์ฉ๋ ๊ฐ๋ฅ์ฑ์ ๋ํด ๊ฒํ ํ๋ค.
์ฒซ๋ฒ์งธ ์์ฐ์ผ๋ก์จ, ๊ณ ์ฃผํ ๊ณ ๋ฆฌ ๋ฐ์ง๊ธฐ์ ๋์ ํ๋ฆฌ์ปค ์ก์์ ์ํ์ํค๊ธฐ ์ํด ๊ธฐ์ค ์ ํธ๋ฅผ ๋ฐฐ์ํํ์ฌ ๋ท๋จ์ ์์ ๊ณ ์ ๋ฃจํ์ ๋์ญํญ์ ํจ๊ณผ์ ์ผ๋ก ๊ทน๋ํ ์ํค๋ ํ๋ก ๊ธฐ์ ์ ์ ์ํ๋ค. ๋ณธ ๊ธฐ์ ์ ์งํฐ๋ฅผ ๋์ ์ํค์ง ์์ผ๋ฉฐ ๋ฐ๋ผ์ ๊นจ๋ํ ์ค๊ฐ ์ฃผํ์ ํด๋ฝ์ ์์ฑ์์ผ ์์ ๊ณ ์ ๋ฃจํ์ ํจ๊ป ๋์ ์ฑ๋ฅ์ ๊ณ ์ฃผํ ํด๋ฝ์ ํฉ์ฑํ๋ค. ๊ธฐ์ค ์ ํธ๋ฅผ ์ฑ๊ณต์ ์ผ๋ก ๋ฐฐ์ํํ๊ธฐ ์ํ ํ์ด๋ฐ ์กฐ๊ฑด๋ค์ ๋จผ์ ๋ถ์ํ์ฌ ํ์ด๋ฐ ์ค๋ฅ๋ฅผ ์ ๊ฑฐํ๊ธฐ ์ํ ๋ฐฉ๋ฒ๋ก ์ ํ์
ํ๋ค. ๊ฐ ๊ต์ ์ค๋์ ์ฐ์ญ์ ํ๋ฅ ์ ๊ธฐ๋ฐ์ผ๋กํ LMS ์๊ณ ๋ฆฌ์ฆ์ ํตํด ๊ฐฑ์ ๋๋๋ก ์ค๊ณ๋๋ค. ๊ต์ ์ ํ์ํ ์๊ฐ์ ์ต์ํ ํ๊ธฐ ์ํ์ฌ, ๊ฐ ๊ต์ ์ด๋์ ํ์ด๋ฐ ์ค๋ฅ ๊ทผ์๋ค์ ํฌ๊ธฐ๋ฅผ ๊ท๋ฉ์ ์ผ๋ก ์ถ๋ก ํ ๊ฐ์ ๋ฐํ์ผ๋ก ์ง์์ ์ผ๋ก ์ ์ด๋๋ค. 40-nm CMOS ๊ณต์ ์ผ๋ก ๊ตฌํ๋ ํ๋กํ ํ์
์นฉ์ ์ธก์ ์ ํตํด ์ ์์, ๊ณ ์ฃผํ ํด๋ฝ์ ๋น ๋ฅธ ๊ต์ ์๊ฐ์์ ํฉ์ฑํด ๋์ ํ์ธํ์๋ค. ์ด๋ 177/223 fs์ rms ์งํฐ๋ฅผ ๊ฐ์ง๋ 8/16 GHz์ ํด๋ฝ์ ์ถ๋ ฅํ๋ค.
๋๋ฒ์งธ ์์ฐ์ผ๋ก์จ, ๊ณ ๋ฆฌ ๋ฐ์ง๊ธฐ์ ๋์ ์ ์ ๋
ธ์ด์ฆ ์์กด์ฑ์ ์ํ์ํค๋ ๊ธฐ์ ์ด ํฌํจ๋ ์ฃผํ์ ํฉ์ฑ๊ธฐ๊ฐ ์ค๊ณ๋์๋ค. ์ด๋ ๊ณ ๋ฆฌ ๋ฐ์ง๊ธฐ์ ์ ์ ํค๋๋ฃธ์ ๋ณด์กดํจ์ผ๋ก์ ๊ณ ์ฃผํ ๋ฐ์ง์ ๊ฐ๋ฅํ๊ฒ ํ๋ค. ๋์๊ฐ, ์ ์ ๋
ธ์ด์ฆ ๊ฐ์ ์ฑ๋ฅ์ ๊ณต์ , ์ ์, ์จ๋ ๋ณ๋์ ๋ํ์ฌ ๋ฏผ๊ฐํ์ง ์์ผ๋ฉฐ, ๋ฐ๋ผ์ ์ถ๊ฐ์ ์ธ ๊ต์ ํ๋ก๋ฅผ ํ์๋ก ํ์ง ์๋๋ค. ๋ง์ง๋ง์ผ๋ก, ์์ ๋
ธ์ด์ฆ์ ๋ํ ํฌ๊ด์ ๋ถ์๊ณผ ํ๋ก ์ต์ ํ๋ฅผ ํตํ์ฌ ์ฃผํ์ ํฉ์ฑ๊ธฐ์ ์ ์ก์ ์ถ๋ ฅ์ ๋ฐฉํดํ์ง ์๋ ๋ฐฉ๋ฒ์ ๊ณ ์ํ์๋ค. ํด๋น ํ๋กํ ํ์
์นฉ์ 40-nm CMOS ๊ณต์ ์ผ๋ก ๊ตฌํ๋์์ผ๋ฉฐ, ์ ์ ๋
ธ์ด์ฆ๊ฐ ์ธ๊ฐ๋์ง ์์ ์ํ์์ 289 fs์ rms ์งํฐ๋ฅผ ๊ฐ์ง๋ 8 GHz์ ํด๋ฝ์ ์ถ๋ ฅํ๋ค. ๋ํ, 20 mVrms์ ์ ์ ๋
ธ์ด์ฆ๊ฐ ์ธ๊ฐ๋์์ ๋์ ์ ๋๋๋ ์งํฐ์ ์์ -23.8 dB ๋งํผ ์ค์ด๋ ๊ฒ์ ํ์ธํ์๋ค.1 Introduction 1
1.1 Motivation 3
1.1.1 Clocking in High-Speed Serial Links 4
1.1.2 Multi-Phase, High-Frequency Clock Conversion 8
1.2 Dissertation Objectives 10
2 RO-Based High-Frequency Synthesis 12
2.1 Phase-Locked Loop Fundamentals 12
2.2 Toward All-Digital Regime 15
2.3 RO Design Challenges 21
2.3.1 Oscillator Phase Noise 21
2.3.2 Challenge 1: High Flicker Noise 23
2.3.3 Challenge 2: High Supply Noise Sensitivity 26
3 Filtering RO Noise 28
3.1 Introduction 28
3.2 Proposed Reference Octupler 34
3.2.1 Delay Constraint 34
3.2.2 Phase Error Calibration 38
3.2.3 Circuit Implementation 51
3.3 IL-ADPLL Implementation 55
3.4 Measurement Results 59
3.5 Summary 63
4 RO Supply Noise Compensation 69
4.1 Introduction 69
4.2 Proposed Analog Closed Loop for Supply Noise Compensation 72
4.2.1 Circuit Implementation 73
4.2.2 Frequency-Domain Analysis 76
4.2.3 Circuit Optimization 81
4.3 ADPLL Implementation 87
4.4 Measurement Results 90
4.5 Summary 98
5 Conclusions 99
A Notes on the 8REF 102
B Notes on the ACSC 105๋ฐ
Engineering evaluations and studies. Volume 3: Exhibit C
High rate multiplexes asymmetry and jitter, data-dependent amplitude variations, and transition density are discussed
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