A low power, low noise, 1.8 GHz voltage-controlled oscillator

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.Includes bibliographical references (leaf 97).by Donald A. Hitko.M.S

ULTRA LOW POWER FSK RECEIVER AND RF ENERGY HARVESTER

This thesis focuses on low power receiver design and energy harvesting techniques as methods for intelligently managing energy usage and energy sources. The goal is to build an inexhaustibly powered communication system that can be widely applied, such as through wireless sensor networks (WSNs). Low power circuit design and smart power management are techniques that are often used to extend the lifetime of such mobile devices. Both methods are utilized here to optimize power usage and sources. RF energy is a promising ambient energy source that is widely available in urban areas and which we investigate in detail. A harvester circuit is modeled and analyzed in detail at low power input. Based on the circuit analysis, a design procedure is given for a narrowband energy harvester. The antenna and harvester co-design methodology improves RF to DC energy conversion efficiency. The strategy of co-design of the antenna and the harvester creates opportunities to optimize the system power conversion efficiency. Previous surveys have found that ambient RF energy is spread broadly over the frequency domain; however, here it is demonstrated that it is theoretically impossible to harvest RF energy over a wide frequency band if the ambient RF energy source(s) are weak, owing to the voltage requirements. It is found that most of the ambient RF energy lies in a series of narrow bands. Two different versions of harvesters have been designed, fabricated, and tested. The simulated and measured results demonstrate a dual-band energy harvester that obtains over 9% efficiency for two different bands (900MHz and 1800MHz) at an input power as low as -19dBm. The DC output voltage of this harvester is over 1V, which can be used to recharge the battery to form an inexhaustibly powered communication system. A new phase locked loop based receiver architecture is developed to avoid the significant conversion losses associated with OOK architectures. This also helps to minimize power consumption. A new low power mixer circuit has also been designed, and a detailed analysis is provided. Based on the mixer, a low power phase locked loop (PLL) based receiver has been designed, fabricated and measured. A power management circuit and a low power transceiver system have also been co-designed to provide a system on chip solution. The low power voltage regulator is designed to handle a variety of battery voltage, environmental temperature, and load conditions. The whole system can work with a battery and an application specific integrated circuit (ASIC) as a sensor node of a WSN network

Design of a Low-Cost Passive UHF RFID tag in 0.18um CMOS technology

The work addresses the design of a passive UHF Radio-Frequency Identification (RFID) tag. In order to realize a product able to be competitive in the RFID expanding market, a cost reduction policy has been applied in the design: a general purpose digital technology has been employed, resorting to specific techniques in order to overcome the limitations due to the lack of process options. Such solutions are accurately described, and every block composing the transponder analog frontend is analyzed, highlighting advantages and disadvantages of the proposed architectures with respect to the ones present in literature. The circuits theory is validated through simulations and experimental data.Il lavoro di tesi è imperniato sul progetto di un tag passivo per l'Identificazione a Radio-Frequenza (RFID) operante nelle bande UHF. Per il progetto è stata applicata una politica di riduzione dei costi, così da proporre un prodotto in grado di essere competitivo nel fiorente mercato dell'RFID: è stata scelta una tecnologia digitale general-purpose, e specifiche tecniche di progettazione sono state utilizzate per superare le limitazioni dovute alla scarsità di opzioni di processo. Le soluzioni adottate sono descritte accuratamente, ed è riportata l'analisi di ogni singolo blocco componente il frontend analogico, evidenziando vantaggi e svantaggi delle architetture proposte rispetto a quelle presenti in letteratura. La validità della teoria alla base dei circuiti è stata verificata tramite simulazioni e dati sperimentali

Giga-hertz CMOS voltage controlled oscillators.

Leung Lai-Kan.Thesis (M.Phil.)--Chinese University of Hong Kong, 2001.Includes bibliographical references (leaves 131-154).Abstracts in English and Chinese.Abstract --- p.iAcknowledgement --- p.iiiTable of Contents --- p.ivList of Figures --- p.ixList of Tables --- p.xvChapter Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Overview --- p.1Chapter 1.2 --- Objectives --- p.2Chapter 1.3 --- Thesis Organization --- p.4Chapter Chapter 2 --- Fundamentals of Voltage Controlled Oscillators --- p.6Chapter 2.1 --- Definition of Commonly Used Figures of Merit --- p.6Chapter 2.1.1 --- Cutoff frequency --- p.6Chapter 2.1.2 --- Center Frequency --- p.8Chapter 2.1.3 --- Tuning Range --- p.8Chapter 2.1.4 --- Tuning Sensitivity --- p.8Chapter 2.1.5 --- Output Power --- p.8Chapter 2.1.6 --- Power Consumption --- p.9Chapter 2.1.7 --- Supply Pulling --- p.9Chapter 2.2 --- Phase Noise --- p.9Chapter 2.2.1 --- Definition of Phase Noise --- p.9Chapter 2.2.2 --- Phase Noise Specification --- p.11Chapter 2.2.3 --- Leeson's formula --- p.12Chapter 2.2.4 --- Models developed by J. Cranincks and M. Steyaert10 --- p.13Chapter 2.2.5 --- Linear Time-Variant Phase Noise Model --- p.13Chapter 2.3 --- Building Blocks of Voltage Controlled Oscillators --- p.17Chapter 2.3.1 --- FETs --- p.17Chapter 2.3.2 --- Varactor --- p.18Chapter 2.3.3 --- Spiral Inductor --- p.21Chapter 2.3.4 --- Modeling of the Spiral Inductor --- p.24Chapter 2.3.5 --- Analysis and Simulation --- p.26Chapter Chapter 3 --- Digital Controlled Oscillator --- p.28Chapter 3.1 --- Introduction --- p.28Chapter 3.2 --- General Principle of Oscillation --- p.28Chapter 3.3 --- Different Oscillator Architectures --- p.30Chapter 3.3.1 --- Single-ended Ring Oscillator --- p.30Chapter 3.3.2 --- Differential Ring Oscillator --- p.32Chapter 3.3.3 --- CMOS Injection-locked Oscillator --- p.33Chapter 3.4 --- Basic Principle of the Injection-locked Oscillator --- p.34Chapter 3.5 --- Digital Controlled Oscillator --- p.36Chapter 3.5.1 --- R-2R Digital-to-Analog Converter --- p.37Chapter 3.6 --- Injection Locking --- p.42Chapter 3.6.1 --- Synchronization Model of the Injection Locked Oscillator --- p.42Chapter 3.7 --- Simulation Results --- p.44Chapter 3.7.1 --- Frequency Tuning Characteristics --- p.44Chapter 3.7.2 --- Phase Noise Performance --- p.47Chapter 3.7.3 --- Locking Characteristics --- p.48Chapter 3.7.4 --- Sensitivity to Supply Voltage and Temperature --- p.48Chapter 3.8 --- Conclusion --- p.49Chapter Chapter 4 --- CMOS LC Voltage Controlled Oscillator --- p.51Chapter 4.1 --- Introduction --- p.51Chapter 4.2 --- LC Oscillator --- p.52Chapter 4.3 --- Circuit Design --- p.54Chapter 4.3.1 --- Oscillation Frequency --- p.55Chapter 4.3.2 --- Oscillation Amplitude --- p.58Chapter 4.3.3 --- Transistor Sizing --- p.59Chapter 4.3.4 --- Power Consumption --- p.62Chapter 4.3.5 --- Tuning Range --- p.62Chapter 4.3.6 --- Phase Noise Analysis --- p.63Chapter 4.4 --- Conclusion --- p.70Chapter Chapter 5 --- LC Quadrature Voltage Controlled Oscillator --- p.71Chapter 5.1 --- Introduction --- p.71Chapter 5.2 --- Conventional CMOS Quadrature LC Voltage Controlled Oscillator --- p.73Chapter 5.3 --- Operational Principle of the CMOS Quadrature LC Voltage Controlled Oscillator --- p.74Chapter 5.3.1 --- General Explanation --- p.74Chapter 5.3.2 --- Mathematical Analysis --- p.75Chapter 5.3.3 --- Drawback of the Conventional CMOS LC Quadrature VCO --- p.77Chapter 5.4 --- Novel CMOS Low Noise Quadrature Voltage Controlled Oscillator --- p.78Chapter 5.4.1 --- Equivalent Output Noise due to the Coupling Transistor --- p.80Chapter 5.4.2 --- Linear Time Varying Model for the Analysis of Total Phase Noise --- p.83Chapter 5.4.3 --- Tuning Range --- p.94Chapter 5.4.4 --- Start-up Condition --- p.95Chapter 5.4.5 --- Power Consumption --- p.97Chapter 5.5 --- New Tuning Mechanism of the Proposed LC Quadrature VCO --- p.98Chapter 5.6 --- Modified Version of the Proposed LC Quadrature Voltage Controlled Oscillator --- p.105Chapter 5.7 --- Conclusion --- p.108Chapter Chapter 6 --- Layout Consideration --- p.109Chapter 6.1 --- Substrate Contacts --- p.109Chapter 6.2 --- Guard Rings --- p.110Chapter 6.3 --- Thermal Noise of the Gate Interconnect --- p.111Chapter 6.4 --- Use of Different Layers of Metal for Interconnection --- p.112Chapter 6.5 --- Slicing of Transistors --- p.113Chapter 6.6 --- Width of Interconnecting Wires and Numbers of Vias --- p.114Chapter 6.7 --- Matching of Devices --- p.114Chapter 6.8 --- Die Micrographs of the Prototypes of the Oscillators --- p.115Chapter Chapter 7 --- Experimental Results --- p.118Chapter 7.1 --- Methodology --- p.118Chapter 7.2 --- Evaluation Board --- p.119Chapter 7.3 --- Measurement Setup --- p.123Chapter 7.4 --- Experimental Results --- p.125Chapter 7.4.1 --- CMOS Injection Locked Oscillator --- p.125Chapter 7.4.2 --- LC Differential Voltage Controlled Oscillator --- p.128Chapter 7.4.3 --- LC Quadrature Voltage Controlled Oscillator --- p.132Chapter 7.5 --- Summary of Performance --- p.139Chapter Chapter 8 --- Conclusion --- p.142Chapter 8.1 --- Contribution --- p.142Chapter 8.2 --- Further Development --- p.143Chapter Chapter 9 --- Appendix --- p.145Chapter 9.1 --- Circuit Transformation --- p.145Chapter 9.2 --- Derivation of the Inductor Model with PGS --- p.146Chapter 9.2.1 --- "Inductance," --- p.146Chapter 9.2.2 --- "Series Resistance, Rs" --- p.146Chapter 9.2.3 --- Series Capacitance --- p.147Chapter 9.2.4 --- Shunt Oxide Capacitance --- p.147Chapter 9.3 --- Calculation of Phase Noise Using the Linear Time Variant Model --- p.148Chapter Chapter 10 --- Bibliography --- p.15

Research on low power technology by AC power supply circuits

制度:新 ; 報告番号:甲3692号 ; 学位の種類:博士(工学) ; 授与年月日:2012/9/15 ; 早大学位記番号:新6060Waseda Universit

Techniques of Energy-Efficient VLSI Chip Design for High-Performance Computing

How to implement quality computing with the limited power budget is the key factor to move very large scale integration (VLSI) chip design forward. This work introduces various techniques of low power VLSI design used for state of art computing. From the viewpoint of power supply, conventional in-chip voltage regulators based on analog blocks bring the large overhead of both power and area to computational chips. Motivated by this, a digital based switchable pin method to dynamically regulate power at low circuit cost has been proposed to make computing to be executed with a stable voltage supply. For one of the widely used and time consuming arithmetic units, multiplier, its operation in logarithmic domain shows an advantageous performance compared to that in binary domain considering computation latency, power and area. However, the introduced conversion error reduces the reliability of the following computation (e.g. multiplication and division.). In this work, a fast calibration method suppressing the conversion error and its VLSI implementation are proposed. The proposed logarithmic converter can be supplied by dc power to achieve fast conversion and clocked power to reduce the power dissipated during conversion. Going out of traditional computation methods and widely used static logic, neuron-like cell is also studied in this work. Using multiple input floating gate (MIFG) metal-oxide semiconductor field-effect transistor (MOSFET) based logic, a 32-bit, 16-operation arithmetic logic unit (ALU) with zipped decoding and a feedback loop is designed. The proposed ALU can reduce the switching power and has a strong driven-in capability due to coupling capacitors compared to static logic based ALU. Besides, recent neural computations bring serious challenges to digital VLSI implementation due to overload matrix multiplications and non-linear functions. An analog VLSI design which is compatible to external digital environment is proposed for the network of long short-term memory (LSTM). The entire analog based network computes much faster and has higher energy efficiency than the digital one

A PLL Design Based on a Standing Wave Resonant Oscillator

In this thesis, we present a new continuously variable high frequency standing wave oscillator and demonstrate its use in generating the phase locked clock signal of a digital IC. The ring based standing wave resonant oscillator is implemented with a plurality of wires connected in a mobius configuration, with a cross coupled inverter pair connected across the wires. The oscillation frequency can be modulated by coarse and fine tuning. Coarse modification is achieved by altering the number of wires in the ring that participate in the oscillation, by driving a digital word to a set of passgates which are connected to each wire in the ring. Fine tuning of the oscillation frequency is achieved by varying the body bias voltage of both the PMOS transistors in the cross coupled inverter pair which sustains the oscillations in the resonant ring. We validated our PLL design in a 90nm process technology. 3D parasitic RLCs for our oscillator ring were extracted with skin effect accounted for. Our PLL provides a frequency locking range from 6 GHz to 9 GHz, with a center frequency of 7.5 GHz. The oscillator alone consumes about 25 mW of power, and the complete PLL consumes a power of 28.5 mW. The observed jitter of the PLL is 2.56 percent. These numbers are significant improvements over the prior art in standing wave based PLLs