A Novel Ultra Low-Power 10T CNFET-Based Full Adder Cell Design in 32nm Technology

Nowadays, energy consumption is the main concern in portable electronic systems such as laptops, smart mobile phones, personal digital assistances (PDAs) and so forth. Considering that the 1-bit Full adder cell has been the determinant circuit due to its wide usage in these systems, it affects the entire performance of the electronic system. In this paper, a novel low-power and low-energy 10 transistor (10T) Full Adder cell using NAND/NOR functions based on carbon nanotube field effect transistors (CNFETs) is presented. The proposed cell showed superiority in terms of power-delay product (PDP) compared to the other cells under different simulation condition, such as power supply, temperature, load and operating frequency variations. Moreover, a Monte Carlo (MC) simulation was conducted to study the reliability of the proposed cell against manufacturing process variations (i.e. the variations of diameters of carbon nanotubes). Simulations confirmed the robustness of the proposed cell

Energy Efficient CNTFET Based Full Adder Using Hybrid Logic

Full Adder is the basic element for arithmetic operations used in Very Large Scale Integrated (VLSI) circuits, therefore, optimization of 1-bit full adder cell improves the overall performance of electronic devices. Due to unique mechanical and electrical characteristics, carbon nanotube field effect transistors (CNTFET) are found to be the most suitable alternative for metal oxide field effect transistor (MOSFET). CNTFET transistor utilizes carbon nanotube (CNT) in the channel region. In this paper, high speed, low power and reduced transistor count full adder cell using CNTFET 32nm technology is presented. Two input full swing XOR gate is designed using 4 transistors which is further used to generate Sum and Carry output signals with the help of Gate-Diffusion-Input (GDI) Technique thus reducing the number of transistors involved. Proposed design simulated in Cadence Virtuoso with 32nm CNTFET technology and results is better design as compared to existing circuits in terms of Power, Delay, Power-Delay-Product (PDP), Energy Consumption and Energy-Delay-Product (EDP)

Variability and reliability analysis of carbon nanotube technology in the presence of manufacturing imperfections

In 1925, Lilienfeld patented the basic principle of field effect transistor (FET). Thirty-four years later, Kahng and Atalla invented the MOSFET. Since that time, it has become the most widely used type of transistor in Integrated Circuits (ICs) and then the most important device in the electronics industry. Progress in the field for at least the last 40 years has followed an exponential behavior in accordance with Moore¿s Law. That is, in order to achieve higher densities and performance at lower power consumption, MOS devices have been scaled down. But this aggressive scaling down of the physical dimensions of MOSFETs has required the introduction of a wide variety of innovative factors to ensure that they could still be properly manufactured. Transistors have expe- rienced an amazing journey in the last 10 years starting with strained channel CMOS transistors at 90nm, carrying on the introduction of the high-k/metal-gate silicon CMOS transistors at 45nm until the use of the multiple-gate transistor architectures at 22nm and at recently achieved 14nm technology node. But, what technology will be able to produce sub-10nm transistors? Different novel materials and devices are being investigated. As an extension and enhancement to current MOSFETs some promising devices are n-type III-V and p-type Germanium FETs, Nanowire and Tunnel FETs, Graphene FETs and Carbon Nanotube FETs. Also, non-conventional FETs and other charge-based information carrier devices and alternative information processing devices are being studied. This thesis is focused on carbon nanotube technology as a possible option for sub-10nm transistors. In recent years, carbon nanotubes (CNTs) have been attracting considerable attention in the field of nanotechnology. They are considered to be a promising substitute for silicon channel because of their small size, unusual geometry (1D structure), and extraordinary electronic properties, including excellent carrier mobility and quasi-ballistic transport. In the same way, carbon nanotube field-effect transistors (CNFETs) could be potential substitutes for MOSFETs. Ideal CNFETs (meaning all CNTs in the transistor behave as semiconductors, have the same diameter and doping level, and are aligned and well-positioned) are predicted to be 5x faster than silicon CMOS, while consuming the same power. However, nowadays CNFETs are also affected by manufacturing variability, and several significant challenges must be overcome before these benefits can be achieved. Certain CNFET manufacturing imperfections, such as CNT diameter and doping variations, mispositioned and misaligned CNTs, high metal-CNT contact resistance, the presence of metallic CNTs (m-CNTs), and CNT density variations, can affect CNFET performance and reliability and must be addressed. The main objective of this thesis is to analyze the impact of the current CNFET manufacturing challenges on multi-channel CNFET performance from the point of view of variability and reliability and at different levels, device and circuit level. Assuming that CNFETs are not ideal or non-homogeneous because of today CNFET manufacturing imperfections, we propose a methodology of analysis that based on a CNFET ideal compact model is able to simulate heterogeneous or non-ideal CNFETs; that is, transistors with different number of tubes that have different diameters, are not uniformly spaced, have different source/drain doping levels, and, most importantly, are made up not only of semiconducting CNTs but also metallic ones. This method will allow us to analyze how CNT-specific variations affect CNFET device characteristics and parameters and CNFET digital circuit performance. Furthermore, we also derive a CNFET failure model and propose an alternative technique based on fault-tolerant architectures to deal with the presence of m-CNTs, one of the main causes of failure in CNFET circuits

Building Efficient and Reliable Emerging Technology Systems

The semiconductor industry has been reaping the benefits of Moore’s law powered by Dennard’s voltage scaling for the past fifty years. However, with the end of Dennard scaling, silicon chip manufacturers are facing a widespread plateau in performance improvements. While the architecture community has focused its effort on exploring parallelism, such as with multi-core, many-core and accelerator-based systems, chip manufacturers have been forced to explore beyond-Moore technologies to improve performance while maintaining power density. Examples of such technologies include monolithic 3D integration, carbon nanotube transistors, tunneling-based transistors, spintronics and quantum computing. However, the infancy of the manufacturing process of these new technologies impedes their usage in commercial products. The goal of this dissertation is to combine both architectural and device-level efforts to provide solutions across the computing stack that can overcome the reliability concerns of emerging technologies. This allows for beyond-Moore systems to compete with highly optimized silicon-based processors, thus, enabling faster commercialization of such systems. This dissertation proposes the following key steps: (i) Multifaceted understanding and modeling of variation and yield issues that occur in emerging technologies, such as carbon nanotube transistors (CNFETs). (ii) Design of systems using suitable logic families such as pass transistor logic that provide high performance. (iii) Design of a multi-granular fault-tolerant reconfigurable architecture that enhances yield and performance. (iv) Design of a multi-technology, multi-accelerator heterogeneous system (v) Development of real-time constrained efficient workload scheduling mechanism for heterogeneous systems. This dissertation first presents the use of pass transistor logic family as an alternate to the CMOS logic family for CNFETs to improve performance. It explores various architectural design choices for CNFETs using pass transistor logic (PTL) to create an energy-efficient RISC-V processor. Our results show that while a CNFET RISC-V processor using CMOS logic achieves a 2.9x energy-delay product (EDP) improvement over a silicon design, using PTL along the critical path components of the processor can boost EDP improvement by 5x as well as reduce area by 17% over 16 nm silicon CMOS. This document further builds on providing fault-tolerant and yield enhancing solutions for emerging 3D integration compatible technologies in the context of CNFETs. The proposed framework can efficiently support high-variation technologies by providing protection against manufacturing defects at multiple granularities: module and pipeline-stage levels. Based on the variation observed in a synthesized design, a reliable CNFET-based 3D multi-granular reconfigurable architecture, 3DTUBE, is presented to overcome the manufacturing difficulties. For 0.4-0.7 V, 3DTUBE provides up to 6.0x higher throughput and 3.1x lower EDP compared to a silicon-based multi-core design evaluated at 1 part per billion transistor failure rate, which is 10,000x lower in comparison to CNFET’s failure rate. This dissertation then ventures into building multi-accelerator heterogeneous systems and real-time schedulers that cater to the requirements of the applications while taking advantage of the underlying heterogeneous system. We introduce optimizations like task pruning, hierarchical hetero-ranking and rank update built upon two scheduler policies (MS-static and MS-dynamic), that result in a performance improvement of 3.5x (average) for real-world autonomous vehicle applications, when compared against state-of-the-art schedulers. Adopting insights from the above work, this thesis presents a multi-accelerator, multi-technology heterogeneous system powered by a multi-constrained scheduler that optimizes for varying task requirements to achieve up to 6.1x better energy over a baseline silicon-based system.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/169699/1/aporvaa_1.pd

Design of Ternary Logic and Arithmetic Circuits Using GNRFET

Multiple valued logic (MVL) can represent an exponentially higher number of data/information compared to the binary logic for the same number of logic bits. Compared to the conventional and other emerging device technologies, Graphene Nano Ribbon Field Effect Transistor (GNRFET) appears to be very promising for designing MVL logic gates and arithmetic circuits due to some exceptional electrical properties of the GNRFET, e.g., the ability to control the threshold voltage by changing the width of the GNR. Variation of the threshold voltage is one of the prescribed techniques to achieve multiple voltage levels to implement the MVL circuit. This paper introduces a design approach for ternary logic gates and circuits using MOS-type GNRFET. The designs of basic ternary logic gates like inverters, NAND, NOR, and ternary arithmetic circuits like the ternary decoder, 3:1 multiplexer, and ternary half-adder are demonstrated using GNRFET. A comparative analysis of the GNRFET based ternary logic gates and circuits and those based on the conventional CMOS and CNTFET technologies is performed using delay, total power, and power-delay-product (PDP) as the metrics. The simulation and analysis are performed using the H-SPICE tool with a GNRFET model available on the Nanohub website

Design of an Efficient Multiplier Using Transistor Level Modified Adders

The endless improvement of modern mobile, compact devices and applications has caused an enormous effect for ultralow power circuit design. Various methods and techniques have been applied successfully to the power, performance region of the design spectrum for lower power consumption. In some applications wherever ultralow power consumption is that the primary requirement and performance is of secondary importance, a more aggressive approach is secure. The new applications mainly depend on the transistor count of circuit with longer economical battery life. The minimum energy point is obtained as an ultralow-power 0.15 V. At this minimal energy point, an ultralow-power 10T 1-bit full adder circuit at sub threshold region and it can be used for energy refrainment applications. It exhibits imperious performance in terms of design standards like average power, propagation delay and transistor count at optimal supply voltage i.e., at 0.15 V. The proposed design uses the 10T 1-bit full adder using 4-bit multiplier compared to conventional 1-bit full adder using 4-bit multiplier circuit. The performance metrics like propagation delay, average power, transistor count are reduced compared to conventional method. The designed 4-bit multiplier is simulated using Tanner tool

Investigation of Multiple-valued Logic Technologies for Beyond-binary Era

Computing technologies are currently based on the binary logic/number system, which is dependent on the simple on and off switching mechanism of the prevailing transistors. With the exponential increase of data processing and storage needs, there is a strong push to move to a higher radix logic/number system that can eradicate or lessen many limitations of the binary system. Anticipated saturation of Moore’s law and the necessity to increase information density and processing speed in the future micro and nanoelectronic circuits and systems provide a strong background and motivation for the beyond-binary logic system. In this review article, different technologies for Multiple-valued-Logic (MVL) devices and the associated prospects and constraints are discussed. The feasibility of the MVL system in real-world applications rests on resolving two major challenges: (i) development of an efficient mathematical approach to implement the MVL logic using available technologies, and (ii) availability of effective synthesis techniques. This review of different technologies for the MVL system is intended to perform a comprehensive investigation of various MVL technologies and a comparative analysis of the feasible approaches to implement MVL devices, especially ternary logic

Multiple-valued logic: technology and circuit implementation

Title from PDF of title page, viewed March 1, 2023Dissertation advisors: Masud H. Chowdhury and Yugyung LeeVitaIncludes bibliographical references (pages 91-107)Dissertation (Ph.D.)--Department of Computer Science and Electrical Engineering. University of Missouri--Kansas City, 2021Computing technologies are currently based on the binary logic/number system, which is dependent on the simple on and off switching mechanism of the prevailing transistors. With the exponential increase of data processing and storage needs, there is a strong push to move to a higher radix logic/number system that can eradicate or lessen many limitations of the binary system. Anticipated saturation of Moore's law and the necessity to increase information density and processing speed in the future micro and nanoelectronic circuits and systems provide a strong background and motivation for the beyond-binary logic system. During this project, different technologies for Multiple-Valued-Logic (MVL) devices and the associated prospects and constraints are discussed. The feasibility of the MVL system in real-world applications rests on resolving two major challenges: (i) development of an efficient mathematical approach to implement the MVL logic using available technologies and (ii) availability of effective synthesis techniques. The main part of this project can be divided into two categories: (i) proposing different novel and efficient design for various logic and arithmetic circuits such as inverter, NAND, NOR, adder, multiplexer etc. (ii) proposing different fast and efficient design for various sequential and memory circuits. For the operation of the device, two of the very promising emerging technologies are used: Graphene Nanoribbon Field Effect Transistor (GNRFET) and Carbon Nano Tube Field Effect Transistor (CNTFET). A comparative analysis of the proposed designs and several state-of-the-art designs are also given in all the cases in terms of delay, total power, and power-delay-product (PDP). The simulation and analysis are performed using the H-SPICE tool with a GNRFET model available on the Nanohub website and CNTFET model available from Standford University website.Introduction -- Fundamentals and scope of multiple valued logic -- Technological aspect of multiple valued logic circuit -- Ternary logic gates using Graphene Nano Ribbon Field Effect Transistor (GNRFET) -- Ternary arithmetic circuits using Graphene Nano Ribbon Field Effect Transistor (GNRFET) -- Ternary sequential circuits using Graphene Nano Ribbon Field Effect Transistor (GNRFET) -- Ternary memory circuits using Carbon Nano Tube Field Effect Transistor (CNTFET) -- Conclusions & future wor

Circuit-level modelling and simulation of carbon nanotube devices

The growing academic interest in carbon nanotubes (CNTs) as a promising novel class of electronic materials has led to significant progress in the understanding of CNT physics including ballistic and non-ballistic electron transport characteristics. Together with the increasing amount of theoretical analysis and experimental studies into the properties of CNT transistors, the need for corresponding modelling techniques has also grown rapidly. This research is focused on the electron transport characteristics of CNT transistors, with the aim to develop efficient techniquesto model and simulate CNT devices for logic circuit analysis.The contributions of this research can be summarised as follows. Firstly, to accelerate the evaluation of the equations that model a CNT transistor, while maintaining high modelling accuracy, three efficient numerical techniques based on piece-wise linear, quadratic polynomial and cubic spline approximation have been developed. The numerical approximation simplifies the solution of the CNT transistor’s self-consistent voltage such that the calculation of the drain-source current is accelerated by at least two orders of magnitude. The numerical approach eliminates complicated calculations in the modelling process and facilitates the development of fast and efficient CNT transistor models for circuit simulation.Secondly, non-ballistic CNT transistors have been considered, and extended circuit-level models which can capture both ballistic and non-ballistic electron transport phenomena, including elastic scattering, phonon scattering, strain and tunnelling effects, have been developed. A salient feature of the developed models is their ability to incorporate both ballistic and non-ballistic transport mechanisms without a significant computational cost. The developed models have been extensively validated against reported transport theories of CNT transistors and experimental results.Thirdly, the proposed carbon nanotube transistor models have been implemented on several platforms. The underlying algorithms have been developed and tested in MATLAB, behaviourallevel models in VHDL-AMS, and improved circuit-level models have been implemented in two versions of the SPICE simulator. As the final contribution of this work, parameter variation analysis has been carried out in SPICE3 to study the performance of the proposed circuit-level CNT transistor models in logic circuit analysis. Typical circuits, including inverters and adders, have been analysed to determine the dependence of the circuit’s correct operation on CNT parameter variation