Supercapacitor assisted LDO (SCALDO) techniquean extra low frequency design approach to high efficiency DC-DC converters and how it compares with the classical switched capacitor converters

Supercapacitor assisted low dropout regulators (SCALDO) were proposed as an alternative design approach to DC-DC converters, where the supercapacitor circulation frequency (switching frequency) is in the order of few Hz to few 10s of Hz, with an output stage based on a low dropout regulator stage. For converters such as 12–5V, 5–3.3V and 5–1.5V, the technique provides efficiency improvement factors of 2, 1.33 and 3 respectively, in compared to linear converters with same input-output combinations. In a 5–1.5V SCALDO regulator, using thin profile supercapacitors in the range of fractional farads to few farads, this translates to an approximate end to end efficiency of near 90%. However, there were concerns that this patented technique is merely a variation of well-known switched capacitor (charge pump) converters. This paper is aimed at providing a broad overview of the capability of SCALDO technique with generalized theory, indicating its capabilities and limitations, and comparing the practical performance with a typical switched capacitor converter of similar current capability

Full On-chip low dropout voltage regulator with an enhanced transient response for low power systems

A full on chip low Dropout Voltage Regulator (LDO) with fast transient response and small capacitor compensation circuit is proposed. The novel technique is implemented to detect the variation voltage at the output of LDO and enable the proposed fast detector amplifier (FDA) to improve load transient response of 50mA load step. The large external capacitor used in Conventional LDO Regulators is removed allowing for greater power system integration for system-on-chip (SoC) applications. The 1.6-V Full On-Chip LDO voltage regulator with a power supply of 1.8 V was designed and simulated in the 0.18µm CMOS technology, consuming only 14 µA of ground current with a fast settling-time LNR(Line Regulation) and LOR(Load regulation) of 928ns and 883ns respectively while the rise and fall times in LNR and LOR is 500ns

Ultra-low Quiescent Current NMOS Low Dropout Regulator With Fast Transient response for Always-On Internet-of-Things Applications

abstract: The increased adoption of Internet-of-Things (IoT) for various applications like smart home, industrial automation, connected vehicles, medical instrumentation, etc. has resulted in a large scale distributed network of sensors, accompanied by their power supply regulator modules, control and data transfer circuitry. Depending on the application, the sensor location can be virtually anywhere and therefore they are typically powered by a localized battery. To ensure long battery-life without replacement, the power consumption of the sensor nodes, the supply regulator and, control and data transmission unit, needs to be very low. Reduction in power consumption in the sensor, control and data transmission is typically done by duty-cycled operation such that they are on periodically only for short bursts of time or turn on only based on a trigger event and are otherwise powered down. These approaches reduce their power consumption significantly and therefore the overall system power is dominated by the consumption in the always-on supply regulator. Besides having low power consumption, supply regulators for such IoT systems also need to have fast transient response to load current changes during a duty-cycled operation. Supply regulation using low quiescent current low dropout (LDO) regulators helps in extending the battery life of such power aware always-on applications with very long standby time. To serve as a supply regulator for such applications, a 1.24 µA quiescent current NMOS low dropout (LDO) is presented in this dissertation. This LDO uses a hybrid bias current generator (HBCG) to boost its bias current and improve the transient response. A scalable bias-current error amplifier with an on-demand buffer drives the NMOS pass device. The error amplifier is powered with an integrated dynamic frequency charge pump to ensure low dropout voltage. A low-power relaxation oscillator (LPRO) generates the charge pump clocks. Switched-capacitor pole tracking (SCPT) compensation scheme is proposed to ensure stability up to maximum load current of 150 mA for a low-ESR output capacitor range of 1 - 47µF. Designed in a 0.25 µm CMOS process, the LDO has an output voltage range of 1V – 3V, a dropout voltage of 240 mV, and a core area of 0.11 mm2.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Analysis on Supercapacitor Assisted Low Dropout (SCALDO) Regulators

State-of-the-art electronic systems employ three fundamental techniques for DC-DC converters: (a) switch-mode power supplies (SMPS); (b) linear power supplies; (c) switched capacitor (charge pump) converters. In practical systems, these three techniques are mixed to provide a complex, but elegant, overall solution, with energy efficiency, effective PCB footprint, noise and transient performance to suit different electronic circuit blocks. Switching regulators have relatively high end-to-end efficiency, in the range of 70 to 93%, but can have issues with output noise and EMI/RFI emissions. Switched capacitor converters use a set of capacitors for energy storage and conversion. In general, linear regulators have low efficiencies in the range 30 to 60%. However, they have outstanding output characteristics such as low noise, excellent transient response to load current fluctuations, design simplicity and low cost design which are far superior to SMPS. Given the complex situation in switch-mode converters, low dropout (LDO) regulators were introduced to address the equirements of noise-sensitive and fast transient loads in portable devices. A typical commercial off-the-shelf LDO has its input voltage slightly higher than the desired regulated output for optimal efficiency. The approximate efficiency of a linear regulator, if the power consumed by the control circuits is negligible, can be expressed by the ratio of Vo/Vin. A very low frequency supercapacitor circulation technique can be combined with commercial low dropout regulator ICs to significantly increase the end-to-end efficiency by a multiplication factor in the range of 1.33 to 3, compared to the efficiency of a linear regulator circuit with the same input-output voltages. In this patented supercapacitor-assisted low dropout (SCALDO) regulator technique developed by a research team at the University of Waikato, supercapacitors are used as lossless voltage droppers, and the energy reuse occurs at very low frequencies in the range of less than ten hertz, eliminating RFI/EMI concerns. This SCALDO technique opens up a new approach to design step-down, DC-DC converters suitable for processor power supplies with very high end-to-end efficiency which is closer to the efficiencies of practical switching regulators, while maintaining the superior output specifications of a linear design. Furthermore, it is important to emphasize that the SCALDO technique is not a variation of well-known switched capacitor DC-DC converters. In this thesis, the basic SCALDO concept is further developed to achieve generalised topologies, with the relevant theory that can be applied to a converter with any input-output step-down voltage combination. For these generalised topologies, some important design parameters, such as the number of supercapacitors, switching matrix details and efficiency improvement factors, are derived to form the basis of designing SCALDO regulators. With the availability of commercial LDO ICs with output current ratings up to 10 A, and thin-prole supercapacitors with DC voltage ratings from 2.3 to 5.5 V, several practically useful, medium-current SCALDO prototypes: 12V-to-5V, 5V-to-2V, 5.5V-to-3.3V have been developed. Experimental studies were carried out on these SCALDO prototypes to quantify performance in terms of line regulation, load regulation, efficiency and transient response. In order to accurately predict the performance and associated waveforms of the individual phases (charge, discharge and transition) of the SCALDO regulator, Laplace transform-based theory for supercapacitor circulation is developed, and analytical predictions are compared with experimental measurements for a 12V-to-5V prototype. The analytical results tallied well with the practical waveforms observed in a 12V-to-5V converter, indicating that the SCALDO technique can be generalized to other versatile configurations, and confirming that the simplified assumptions used to describe the circuit elements are reasonable and justifiable. After analysing the performance of several SCALDO prototypes, some practical issues in designing SCALDO regulators have been identified. These relate to power losses and implications for future development of the SCALDO design

CMOS Design of Reconfigurable SoC Systems for Impedance Sensor Devices

La rápida evolución en el campo de los sensores inteligentes, junto con los avances en las tecnologías de la computación y la comunicación, está revolucionando la forma en que recopilamos y analizamos datos del mundo físico para tomar decisiones, facilitando nuevas soluciones que desempeñan tareas que antes eran inconcebibles de lograr.La inclusión en un mismo dado de silicio de todos los elementos necesarios para un proceso de monitorización y actuación ha sido posible gracias a los avances en micro (y nano) electrónica. Al mismo tiempo, la evolución de las tecnologías de procesamiento y micromecanizado de superficies de silicio y otros materiales complementarios ha dado lugar al desarrollo de sensores integrados compatibles con CMOS, lo que permite la implementación de matrices de sensores de alta densidad. Así, la combinación de un sistema de adquisición basado en sensores on-Chip, junto con un microprocesador como núcleo digital donde se puede ejecutar la digitalización de señales, el procesamiento y la comunicación de datos proporciona características adicionales como reducción del coste, compacidad, portabilidad, alimentación por batería, facilidad de uso e intercambio inteligente de datos, aumentando su potencial número de aplicaciones.Esta tesis pretende profundizar en el diseño de un sistema portátil de medición de espectroscopía de impedancia de baja potencia operado por batería, basado en tecnologías microelectrónicas CMOS, que pueda integrarse con el sensor, proporcionando una implementación paralelizable sin incrementar significativamente el tamaño o el consumo, pero manteniendo las principales características de fiabilidad y sensibilidad de un instrumento de laboratorio. Esto requiere el diseño tanto de la etapa de gestión de la energía como de las diferentes celdas que conforman la interfaz, que habrán de satisfacer los requisitos de un alto rendimiento a la par que las exigentes restricciones de tamaño mínimo y bajo consumo requeridas en la monitorización portátil, características que son aún más críticas al considerar la tendencia actual hacia matrices de sensores.A nivel de celdas, se proponen diferentes circuitos en un proceso CMOS de 180 nm: un regulador de baja caída de voltaje como unidad de gestión de energía, que proporciona una alimentación de 1.8 V estable, de bajo ruido, precisa e independiente de la carga para todo el sistema; amplificadores de instrumentación con una aproximación completamente diferencial, que incluyen una etapa de entrada de voltaje/corriente configurable, ganancia programable y ancho de banda ajustable, tanto en la frecuencia de corte baja como alta; un multiplicador para conformar la demodulación dual, que está embebido en el amplificador para optimizar consumo y área; y filtros pasa baja totalmente integrados, que actúan como extractores de magnitud de DC, con frecuencias de corte ajustables desde sub-Hz hasta cientos de Hz.<br /

A fully on-chip LDO voltage regulator with 37 dB PSRR at 1 MHz for remotely powered biomedical implants

This article presents a fully on-chip low-power LDO voltage regulator dedicated to remotely powered wireless cortical implants. This regulator is stable over the full range of alternating load current and provides fast load regulation achieved by applying a time-domain design methodology. Moreover, a new compensation technique is proposed and implemented to improve PSRR beyond the performance levels which can be obtained using the standard cascode compensation technique. Measurement results show that the regulator has a load regulation of 0.175 V/A, a line regulation of 0.024%, and a PSRR of 37 dB at 1MHz power carrier frequency. The output of the regulator settles within 10-bit accuracy of the nominal voltage (1.8 V) within 1.6μs, at full load transition. The total ground current including the bandgap reference circuit is 28μA and the active chip area measures 290μm×360μm in a 0.18μm CMOS technolog

LDO compensation with variable Miller series resistance

A new compensation method for low dropout (LDO) voltage regulators is proposed, where the series resistor of the conventional Miller compensation changes with the load current to track the variations in the first non‐dominant pole

Low-Power Fast-Settling Low-Dropout Regulator Using a Digitally Assisted Voltage Accelerator for DVFS Application

[[abstract]]This paper presents a low-power fast-settling low-dropout regulator (LDO) using a digitally assisted voltage accelerator. Using the selectable-voltage control technique and digitally assisted voltage accelerator significantly improves the transition response time within output voltage switched. The proposed LDO regulator uses the selectable-voltage control technique to provide two selectable-voltage outputs of 2.5 V and 1.8 V. Using the digitally assisted voltage accelerator when the output voltage is switched reduces the settling time. The simulation results show that the settling time of the proposed LDO regulator is significantly reduced from 4.2 ms to 15.5 μs. Moreover, the selectable-voltage control unit and the digitally assisted voltage accelerator of the proposed LDO regulator consume only 0.54 mW under a load current of 100 mA. Therefore, the proposed LDO regulator is suitable for low-power dynamic voltage and frequency-scaling applications.[[notice]]補正完畢[[incitationindex]]EI[[booktype]]紙

High Performance Power Management Integrated Circuits for Portable Devices

abstract: Portable devices often require multiple power management IC (PMIC) to power different sub-modules, Li-ion batteries are well suited for portable devices because of its small size, high energy density and long life cycle. Since Li-ion battery is the major power source for portable device, fast and high-efficiency battery charging solution has become a major requirement in portable device application. In the first part of dissertation, a high performance Li-ion switching battery charger is proposed. Cascaded two loop (CTL) control architecture is used for seamless CC-CV transition, time based technique is utilized to minimize controller area and power consumption. Time domain controller is implemented by using voltage controlled oscillator (VCO) and voltage controlled delay line (VCDL). Several efficiency improvement techniques such as segmented power-FET, quasi-zero voltage switching (QZVS) and switching frequency reduction are proposed. The proposed switching battery charger is able to provide maximum 2 A charging current and has an peak efficiency of 93.3%. By configure the charger as boost converter, the charger is able to provide maximum 1.5 A charging current while achieving 96.3% peak efficiency. The second part of dissertation presents a digital low dropout regulator (DLDO) for system on a chip (SoC) in portable devices application. The proposed DLDO achieve fast transient settling time, lower undershoot/overshoot and higher PSR performance compared to state of the art. By having a good PSR performance, the proposed DLDO is able to power mixed signal load. To achieve a fast load transient response, a load transient detector (LTD) enables boost mode operation of the digital PI controller. The boost mode operation achieves sub microsecond settling time, and reduces the settling time by 50% to 250 ns, undershoot/overshoot by 35% to 250 mV and 17% to 125 mV without compromising the system stability.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

High power-supply rejection current-mode low-dropout linear regulator

Power management components can be found in a host of different applications ranging from portable hand held gadgets to modern avionics to advanced medical instrumentations, among many other applications. Low-dropout (LDO) linear regulators are particularly popular owing to their: ease of use, low cost, high accuracy, low noise, and high bandwidth. With all its glory, however, it tends to underperform switched-mode power supplies (SMPS) when with comes to power conversion efficiency, although the later generates a lot of ripple at its output. With the growing need to improve system efficiency (hence longer battery life) without degrading system performance, many high end (noise sensitive) applications such as data converters, RF transceivers, precision signal conditioning, among others, use high efficiency SMPS with LDO regulators as post-regulators for rejecting the ripple generated by SMPS. This attribute of LDO regulators is known as power supply rejection (PSR). With the trend towards increasing switching frequency for SMPS, to minimize PC board real estate, it is becoming ever more difficult for LDO regulators to suppress the associate high frequency ripple since at such high frequencies, different parasitic components of the LDO regulator start to deteriorate its PSR performance. There have been a handful of different techniques suggested in the literature that can be used to achieve good PSR performance at higher frequencies. However, each of these techniques suffers from a number of drawbacks ranging from reduced efficiency to increased cost to increased solution size, and with the growing demand for higher efficiency and smaller power supplies, these techniques have their clear limitations. The objective of this research project is to develop a novel current-mode LDO regulator that can achieve good high frequency PSR performance without suffering from the afore mentioned drawbacks. The proposed architecture was fabricated using a proprietary 1.5 um Bipolar process technology, and the measurement results show a PSR improvement of 20dB (at high frequencies) over conventional regulators. Moreover, the proposed LDO regulator requires a small 15nF output capacitor for stability, which is far smaller than some of the currently used techniques.M.S.Committee Chair: Rincón-Mora, Gabriel; Committee Member: Ghovanloo, Maysam; Committee Member: Leach, W. Marshal