Single-input Multiple-output Tunable Log-domain Current-mode Universal Filter

This paper describes the design of a current-mode single-input multiple-output (SIMO) universal filter based on the log-domain filtering concept. The circuit is a direct realization of a first-order differential equation for obtaining the lossy integrator circuit. Lossless integrators are realized by log-domain lossy integrators. The proposed filter comprises only two grounded capacitors and twenty-four transistors. This filter suits to operate in very high frequency (VHF) applications. The pole-frequency of the proposed filter can be controlled over five decade frequency range through bias currents. The pole-Q can be independently controlled with the pole-frequency. Non-ideal effects on the filter are studied in detail. A validated BJT model is used in the simulations operated by a single power supply, as low as 2.5 V. The simulation results using PSpice are included to confirm the good performances and are in agreement with the theory

A wideband linear tunable CDTA and its application in field programmable analogue array

This document is the Accepted Manuscript version of the following article: Hu, Z., Wang, C., Sun, J. et al. ‘A wideband linear tunable CDTA and its application in field programmable analogue array’, Analog Integrated Circuits and Signal Processing, Vol. 88 (3): 465-483, September 2016. Under embargo. Embargo end date: 6 June 2017. The final publication is available at Springer via https://link.springer.com/article/10.1007%2Fs10470-016-0772-7 © Springer Science+Business Media New York 2016In this paper, a NMOS-based wideband low power and linear tunable transconductance current differencing transconductance amplifier (CDTA) is presented. Based on the NMOS CDTA, a novel simple and easily reconfigurable configurable analogue block (CAB) is designed. Moreover, using the novel CAB, a simple and versatile butterfly-shaped FPAA structure is introduced. The FPAA consists of six identical CABs, and it could realize six order current-mode low pass filter, second order current-mode universal filter, current-mode quadrature oscillator, current-mode multi-phase oscillator and current-mode multiplier for analog signal processing. The Cadence IC Design Tools 5.1.41 post-layout simulation and measurement results are included to confirm the theory.Peer reviewedFinal Accepted Versio

Implementing Homeostatic Plasticity in Analog VLSI

Neuromorphic engineering systems are electronic devices that emulate the spike based computational paradigm. CMOS processes scaling yield mismatch and non-ideality that limit the performances of the device. A neuromorphic approach to address this problem is to implement the SHP in silicon. The SHP is implemented by an AGC with a LPF with long time constants. Given such LPF challenging specifications, I developed a compact CMOS filter architecture based on leakages currents in a pMOS deviceopenEmbargo per motivi di segretezza e/o di proprietà dei risultati e/o informazioni sensibil

Low-voltage CMOS log-companding techniques for audio applications

This paper presents a collection of novel current-mode circuit techniques for the integration of very low-voltage (down to 1 V) low-power (few hundreds of μA) complete SoCs in CMOS technologies. The new design proposal is based on both, the Log Companding theory and the MOSFET operating in subthreshold. Several basic building blocks for audio amplification, AGC and arbitrary filtering are given. The feasibility of the proposed CMOS circuits is illustrated through experimental data for different design case studies in 1.2 and 0.35 μm VLSI technologies.Comisión Interministerial de Ciencia y Tecnología TIC97-1159, TIC99- 1084European Union ESPRIT-FUSE-2306

A Modular Programmable CMOS Analog Fuzzy Controller Chip

We present a highly modular fuzzy inference analog CMOS chip architecture with on-chip digital programmability. This chip consists of the interconnection of parameterized instances of two different kind of blocks, namely label blocks and rule blocks. The architecture realizes a lattice partition of the universe of discourse, which at the hardware level means that the fuzzy labels associated to every input (realized by the label blocks) are shared among the rule blocks. This reduces the area and power consumption and is the key point for chip modularity. The proposed architecture is demonstrated through a 16-rule two input CMOS 1-μm prototype which features an operation speed of 2.5 Mflips (2.5×10^6 fuzzy inferences per second) with 8.6 mW power consumption. Core area occupation of this prototype is of only 1.6 mm 2 including the digital control and memory circuitry used for programmability. Because of the architecture modularity the number of inputs and rules can be increased with any hardly design effort.This work was supported in part by the Spanish C.I.C.Y.T under Contract TIC96-1392-C02- 02 (SIVA)