Dynamic calibration of current-steering DAC

The demand for high-speed communication systems has dramatically increased during the last decades. Working as an interface between the digital and analog world, Digital-to-Analog converters (DACs) are becoming more and more important because they are a key part which limits the accuracy and speed of an overall system. Consequently, the requirements for high-speed and high-accuracy DACs are increasingly demanding. It is well recognized that dynamic performance of the DACs degrades dramatically with increasing input signal frequencies and update rates. The dynamic performance is often characterized by the spurious free dynamic range (SFDR). The SFDR is determined by the spectral harmonics, which are attributable to system nonlinearities.;A new calibration approach is presented in this thesis that compensates for the dynamic errors in performance. In this approach, the nonlinear components of the input dependent and previous input code dependent errors are characterized, and correction codes that can be used to calibrate the DAC for these nonlinearities are stored in a two-dimensional error look-up table. A series of pulses is generated at run time by addressing the error look-up table with the most significant bits of the Boolean input and by using the corresponding output to drive a calibration DAC whose output is summed with the original DAC output. The approach is applied at both the behavioral level and the circuit level in current-steering DAC.;The validity of this approach is verified by simulation. These simulations show that the dynamic nonlinearities can be dramatically reduced with this calibration scheme. The simulation results also show that this calibration approach is robust to errors in both the width and height of calibration pulses.;Experimental measurement results are also provided for a special case of this dynamic calibration algorithm that show that the dynamic performance can be improved through dynamic calibration, provided the mean error values in the table are close to their real values

Design and Optimization of Low-power Level-crossing ADCs

This thesis investigates some of the practical issues related to the implementation of level-crossing ADCs in nanometer CMOS. A level-crossing ADC targeting minimum power is designed and measured. Three techniques to circumvent performance limitations due to the zero-crossing detector at the heart of the ADC are proposed and demonstrated: an adaptive resolution algorithm, an adaptive bias current algorithm, and automatic offset cancelation. The ADC, fabricated in 130 nm CMOS, is designed to operate over a 20 kHz bandwidth while consuming a maximum of 8.5 uW. A peak SNDR of 54 dB for this 8-bit ADC demonstrates a key advantage of level-crossing sampling, namely SNDR higher than the classic Nyquist limit

Wideband CMOS Data Converters for Linear and Efficient mmWave Transmitters

With continuously increasing demands for wireless connectivity, higher\ua0carrier frequencies and wider bandwidths are explored. To overcome a limited transmit power at these higher carrier frequencies, multiple\ua0input multiple output (MIMO) systems, with a large number of transmitters\ua0and antennas, are used to direct the transmitted power towards\ua0the user. With a large transmitter count, each individual transmitter\ua0needs to be small and allow for tight integration with digital circuits. In\ua0addition, modern communication standards require linear transmitters,\ua0making linearity an important factor in the transmitter design.In this thesis, radio frequency digital-to-analog converter (RF-DAC)-based transmitters are explored. They shift the transition from digital\ua0to analog closer to the antennas, performing both digital-to-analog\ua0conversion and up-conversion in a single block. To reduce the need for\ua0computationally costly digital predistortion (DPD), a linear and wellbehaved\ua0RF-DAC transfer characteristic is desirable. The combination\ua0of non-overlapping local oscillator (LO) signals and an expanding segmented\ua0non-linear RF-DAC scaling is evaluated as a way to linearize\ua0the transmitter. This linearization concept has been studied both for\ua0the linearization of the RF-DAC itself and for the joint linearization of\ua0the cascaded RF-DAC-based modulator and power amplifier (PA) combination.\ua0To adapt the linearization, observation receivers are needed.\ua0In these, high-speed analog-to-digital converters (ADCs) have a central\ua0role. A high-speed ADC has been designed and evaluated to understand\ua0how concepts used to increase the sample rate affect the dynamic performance

Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications

As the data rates of wireline communication links increases, channel impairments such as skin effect, dielectric loss, fiber dispersion, reflections and cross-talk become more pronounced. This warrants more interest in analog-to-digital converter (ADC)-based serial link receivers, as they allow for more complex and flexible back-end digital signal processing (DSP) relative to binary or mixed-signal receivers. Utilizing this back-end DSP allows for complex digital equalization and more bandwidth-efficient modulation schemes, while also displaying reduced process/voltage/temperature (PVT) sensitivity. Furthermore, these architectures offer straightforward design translation and can directly leverage the area and power scaling offered by new CMOS technology nodes. However, the power consumption of the ADC front-end and subsequent digital signal processing is a major issue. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-effcient receiver. This dissertation presents efficient implementations for multi-GS/s time-interleaved ADCs with partial embedded equalization. First prototype details a 6b 1.6GS/s ADC with a novel embedded redundant-cycle 1-tap DFE structure in 90nm CMOS. The other two prototypes explain more complex 6b 10GS/s ADCs with efficiently embedded feed-forward equalization (FFE) and decision feedback equalization (DFE) in 65nm CMOS. Leveraging a time-interleaved successive approximation ADC architecture, new structures for embedded DFE and FFE are proposed with low power/area overhead. Measurement results over FR4 channels verify the effectiveness of proposed embedded equalization schemes. The comparison of fabricated prototypes against state-of-the-art general-purpose ADCs at similar speed/resolution range shows comparable performances, while the proposed architectures include embedded equalization as well

Design and implementation of 4 bit binary weighted current steering DAC

A compact current-mode Digital-to-Analog converter (DAC) suitable for biomedical application is repesented in this paper .The designed DAC is binary weighted in 180nm CMOS technology with 1.8V supply voltage. In this implementation, authors have focused on calculaton of Non linearity error say INL and DNL for 4 bit DAC having various type of switches: NMOS, PMOS and Transmission Gate. The implemented DAC uses lower area and power compared to unary architecture due to absence of digital decoders. The desired value of Integrated non linearity (INL) and Differential non linearity (DNL) for DAC for are within a range of +0.5LSB. Result obtained in this works for INL and DNL for the case DAC using Transmission Gate is +0.34LSB and +0.38 LSB respectively with 22mW power dissipation

Design Automation of Low Power Circuits in Nano-Scale CMOS and Beyond-CMOS Technologies.

Today’s integrated system on chips (SoCs) usually consist of billions of transistors accounting for both digital and analog blocks. Integrating such massive blocks on a single chip involves several challenges, especially when transferring analog blocks from an older technology to newer ones. Furthermore, the exponential growth for IoT devices necessitates small and low power circuits. Hence, new devices and architectures must be investigated to meet the power and area constraints for wireless sensor networks (WSNs). In such cases, design automation becomes an essential tool to reduce the time to market of the circuits. This dissertation focuses on automating the design process of analog designs in advanced CMOS technology nodes, as well as reciprocal quantum logic (RQL) superconducting circuits. For CMOS analog circuits, our design automation technique employs digital automatic placement and routing tools to synthesize and lay out analog blocks along with digital blocks in a cell-based design approach. This technique was demonstrated in the design of a digital-to-analog converter. In the domain of RQL circuits, the automated design of several functional units of a commercial Processor is presented. These automation techniques enable the design of VLSI-scale circuits in this technology. In addition to the investigation of new technologies, several new baseband signal processor architectures are presented in this dissertation. These architectures are suitable for low-power mm3-scale WSNs and enable high frequency transceivers to operate within the power constraints of standalone IoT nodes.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/133177/1/elnaz_1.pd

ASIC para estimulação elétrica da espinal medula

Spinal Cord Injuries (SCI) have severe consequences such as tetraplegia and paraplegia, which dramatically affect the healthcare of the patients. Successful therapies for such injuries are yet to be attainable. Currently, there is a focus on the study and implementation of small implantable devices that are capable of providing in-vivo electrical stimulation to the spinal cord. Since the impedance of the neural tissue experiences constant changes, the focus is on using current stimulation instead of voltage, to compensate the impedance variations. Furthermore, the usage of scaffolds to provide alignment on the regrown fibers, combined with electrical stimulation is viewed as possible solution for SCI therapy. The NeuroStim- Spinal project, in which this work is inserted, aims to propose a SCI therapy based on in-vivo electrical stimulation combined with 3D printed scaffolds that have in its composition based materials (GBM) and adipose derived decellularized tissue (adECM). The work presented is an application-specific integrated circuit design (ASIC) that provides current-mode stimulation for neuronal regeneration, with the objective of providing in-vivo electrical stimulation for SCI therapy. The main challenges on the design of such devices is in obtaining low circuit area and power consumption, while maintaining the specifications needed. These characteristics are important, since it is intended to be an implantable device. The stimulation circuit consists of, a communication interface with a microcontroller using the Serial Peripheral Communication (SPI) protocol, a 10-bit DAC (Digital-to-Analog Converter) based on a binary charge scaling architecture, a voltage-to-current converter with a feed-forward voltage attenuator (FFVA) architecture, and a H-bridge circuit composed of CMOS switches to drive the scaffold. Results demonstrate that the system developed is capable of driving current from 0 to 200μA with an absolute error bellow 0.75μA. In addition, the developed circuit can provide these range of currents with high linearity to a 15k load impedance. The system can still provide linear stimulation for higher load impedance’s, but in smaller current ranges. Furthermore, the circuit uses a supply voltage of 5V and has an average power dissipation of 19.5mW. The ASIC was developed using a 0.35μm CMOS technology, has dimensions of 270μm per 700μm, which corresponds to a total area of 0.19mm2. The work was developed using the Cadence software.Lesões na Medula Espinhal são causadas sobretudo devido acidentes rodoviários, quedas e lesões na prática de desportos. Estas têm graves consequências no estado de saúde dos pacientes, uma vez que saõ responsáveis por diagnósticos como tetraplegia e paraplegia. Até hoje, terapias eficazes para este tipo de lesões ainda não foram conseguidas, o que torna esta temática num foco de estudo. Atualmente, uma das orientações deste foco de estudo está direcionado em dispositivos elétricos implantáveis capazes de estimular a espinal medula in-vivo, promovendo a regeneração da mesma. Adicionalmente, o uso de materiais (scaffolds) que permitem manter o alinhemento no crescimento das fibras, em conjunto com estimulação elétrica é vista como a solução consensual para terapias relacionadas com Lesões na Medula Espinhal. Assim, o projeto NeuroStimSpinal, na qual este trabalho se insere, foi proposto. Este tem como objetivo propor uma terapia para esta problemática usando estimulação elétrica em conjunto com scaffolds impressas em 3D. O trabalho apresentado nesta dissertação é baseado num circuito integrado de aplicação específica (CIAE) para estimulação em corrente da espinal medula, com o intuito de promover a regeneração da mesma. Os desafios na implementação deste tipo de circuitos estão relacionados com a necessidade destes terem de ser pequenos em tamanho e consumir uma potência reduzida, mantendo as características necessárias para a estimulação, uma vez que é necessário que o mesmo faça parte de um dispositivo implantável. O circuito de estimulação proposto consiste: numa interface de comunicação com a unidade de controlo (microcontrolador) usando o protocolo Serial Peripheral Communication (SPI); um conversor digital para analógico de 10 bits, o qual se baseia numa arquitetura de escalonamento binário por carga; um conversor tensão para corrente rail-to-rail e uma ponte H que direciona a corrente pela scaffold, cuja implementação se baseia no uso de portas de transmissão como comutadores. Resultados ao trabalho desenvolvido mostram que o circuito é capaz de estimular a scaffold com correntes entre 0 to 200μA com um erro na corrente de estimulação inferior a 0.75μA. O circuito é capaz ainda de fornecer uma corrente linear, na gama mencionada, a cargas com impedancias até 15k . Para cargas superiores o circuito é capaz de fornecer uma corrente linear, embora em gamas de correntes menores. O circuito implementado usa como tensão de alimentação 5V, tem um consumo médio de potência de 19.5mW e ocupa uma área de 0.19mm2. No decurso do trabalho desenvolvido foi utilizada uma tecnlogoia CMOS de 0.35um. A implementação e resultados foram obtidos com recurso ao software Cadence.Mestrado em Engenharia Eletrónica e Telecomunicaçõe

Design of High-Speed Power-Efficient A/D Converters for Wireline ADC-Based Receiver Applications

Serial input/output (I/O) data rates are increasing in order to support the explosion in network traffic driven by big data applications such as the Internet of Things (IoT), cloud computing and etc. As the high-speed data symbol times shrink, this results in an increased amount of inter-symbol interference (ISI) for transmission over both severe low-pass electrical channels and dispersive optical channels. This necessitates increased equalization complexity and consideration of advanced modulation schemes, such as four-level pulse amplitude modulation (PAM-4). Serial links which utilize an analog-to-digital converter (ADC) receiver front-end offer a potential solution, as they enable more powerful and flexible digital signal processing (DSP) for equalization and symbol detection and can easily support advanced modulation schemes. Moreover, the DSP back-end provides robustness to process, voltage, and temperature (PVT) variations, benefits from improved area and power with CMOS technology scaling and offers easy design transfer between different technology nodes and thus improved time-to-market. However, ADC-based receivers generally consume higher power relative to their mixed-signal counterparts because of the significant power consumed by conventional multi-GS/s ADC implementations. This motivates exploration of energy-efficient ADC designs with moderate resolution and very high sampling rates to support data rates at or above 50Gb/s. This dissertation presents two power-efficient designs of ≥25GS/s time-interleaved ADCs for ADC-based wireline receivers. The first prototype includes the implementation of a 6b 25GS/s time-interleaved multi-bit search ADC in 65nm CMOS with a soft-decision selection algorithm that provides redundancy for relaxed track-and-hold (T/H) settling and improved metastability tolerance, achieving a figure-of-merit (FoM) of 143fJ/conversion step and 1.76pJ/bit for a PAM-4 receiver design. The second prototype features the design of a 52Gb/s PAM-4 ADC-based receiver in 65nm CMOS, where the front-end consists of a 4-stage continuous-time linear equalizer (CTLE)/variable gain amplifier (VGA) and a 6b 26GS/s time-interleaved SAR ADC with a comparator-assisted 2b/stage structure for reduced digital-to-analog converter (DAC) complexity and a 3-tap embedded feed-forward equalizer (FFE) for relaxed ADC resolution requirement. The receiver front-end achieves an efficiency of 4.53bJ/bit, while compensating for up to 31dB loss with DSP and no transmitter (TX) equalization