A 1.67 pJ/Conversion-step 8-bit SAR-Flash ADC Architecture in 90-nm CMOS Technology

A novice advanced architecture of 8-bit analog todigital converter is introduced and analyzed in this work. Thestructure of proposed ADC is based on the sub-ranging ADCarchitecture in which a 4-bit resolution flash-ADC is utilized. Theproposed ADC architecture is designed by employing a comparatorwhich is equipped with common mode current feedback andgain boosting technique (CMFD-GB) and a residue amplifier. Theproposed 8 bits ADC structure can achieve the speed of 140 megasamplesper second. The proposed ADC architecture is designedat a resolution of 8 bits at 10 MHz sampling frequency. DNL andINL values of the proposed design are -0.94/1.22 and -1.19/1.19respectively. The ADC design dissipates a power of 1.24 mWwith the conversion speed of 0.98 ns. The magnitude of SFDRand SNR from the simulations at Nyquist input is 39.77 and 35.62decibel respectively. Simulations are performed on a SPICE basedtool in 90 nm CMOS technology. The comparison shows betterperformance for the proposed ADC design in comparison toother ADC architectures regarding speed, resolution and powerconsumption

Proposal for an 8-bit Radiation Hardened Flash A/d Converter

Electrical Engineerin

Adaptation in Standard CMOS Processes with Floating Gate Structures and Techniques

We apply adaptation into ordinary circuits and systems to achieve high performance, high quality results. Mismatch in manufactured VLSI devices has been the main limiting factor in quality for many analog and mixed-signal designs. Traditional compensation methods are generally costly. A few examples include enlarging the device size, averaging signals, and trimming with laser. By applying floating gate adaptation to standard CMOS circuits, we demonstrate here that we are able to trim CMOS comparator offset to a precision of 0.7mV, reduce CMOS image sensor fixed-pattern noise power by a factor of 100, and achieve 5.8 effective number of bits (ENOB) in a 6-bit flash analog-to-digital converter (ADC) operating at 750MHz. The adaptive circuits generally exhibit special features in addition to an improved performance. These special features are generally beyond the capabilities of traditional CMOS design approaches and they open exciting opportunities in novel circuit designs. Specifically, the adaptive comparator has the ability to store an accurate arbitrary offset, the image sensor can be set up to memorize previously captured scenes like a human retina, and the ADC can be configured to adapt to the incoming analog signal distribution and perform an efficient signal conversion that minimizes distortion and maximizes output entropy

Aportaciones al diseño de ADCs en tecnologías nanométricas y para entornos de alta radiación

El trabajo presentado a lo largo de esta Tesis Doctoral está intrínsecamente relacionado con la evolución del diseño de circuitos integrados analógicos y de señal mixta empleando tecnologías nanométricas. En los últimos años, el desarrollo de dichas tecnologías ha posibilitado un avance gigantesco en cuanto a funcionalidad y velocidad de los sistemas de comunicaciones, provocando un gran auge en los sistemas de comunicaciones, con especial relevancia de los estándares inalámbricos. No obstante, también han surgido nuevos retos a nivel arquitectural y de diseño derivados, en gran medida, de los efectos del escalado tecnológico, que obligan a la búsqueda de nuevas soluciones para adecuarse a unas restricciones cada vez más exigentes. En la presente Tesis Doctoral se han realizado aportaciones en dos ámbitos destinados a aplicaciones de interés para el diseño microelectrónico analógico en tecnologías nanométricas: 1. Diseño de convertidores Analógico-Digital de muy alta velocidad. Los nuevos estándares de comunicaciones de banda ancha o la mayor velocidad de lectura de los soportes de almacenamiento de información incrementan la necesidad de mayor velocidad de conversión en el diseño de convertidores Analógico-Digital (A/D). Los convertidores con arquitectura flash o de conversión directa suelen ser los más utilizados para este tipo de aplicaciones. Sin embargo, la resolución de dichos convertidores se ve seriamente comprometida por el error de offset de los comparadores utilizados, que en tecnologías nanométricas resulta especialmente sensible a las variaciones de procesos. Las prestaciones de las técnicas tradicionales se ven afectadas por los efectos del escalado, siendo necesario emplear nuevas técnicas que permitan alcanzar los requerimientos con un consumo energético eficiente. 2. Diseño robusto de circuitos analógicos para aplicaciones espaciales y nucleares. Las frecuencias de trabajo cada vez más elevadas y dimensiones de los transistores más y más pequeñas hacen que la influencia de los Efectos de Eventos Singulares (SEE) sea cada vez más crítica, tanto en los circuitos digitales como analógicos. La evolución de las tecnologías CMOS ha contribuido a incrementar los riesgos de errores críticos en circuitos en entornos de alta radiación, donde la interacción de iones pesados con los componentes analógicos puede dar lugar a variaciones transitorias o permanentes en su comportamiento. Por una parte, las frecuencias de funcionamiento cada vez más altas pueden incrementar la sensibilidad ante la captura de Eventos Singulares Transitorios (SET), aumentando el riesgo de propagación de errores. Además, los SET son fuertemente dependientes de la configuración eléctrica de los dispositivos, pudiendo afectar muy seriamente al rendimiento e incluso a la funcionalidad de los circuitos. Es por ello que el estudio de estos impactos y su influencia en circuitos analógicos ha adquirido en los últimos años una enorme relevancia, ya que un análisis de las posibles vulnerabilidades puede proporcionar información clave para el diseño de sistemas robustos contra la radiación. Dentro del primer ámbito de investigación se ha diseñado un convertidor A/D de 6 bits de tipo flash para el estándar de comunicaciones Ultra-WideBand (UWB). En primer lugar, se han estudiado de las limitaciones que imponen las tecnologías nanométricas con vistas a su aplicación al diseño microelectrónico en convertidores de alta velocidad y bajo consumo. Se ha determinado que el comportamiento de los convertidores A/D de tipo flash está limitado por errores causados por las mayores variaciones en los procesos. Mediante el análisis de la literatura, se han estudiado e identificado diferentes técnicas y tendencias seguidas por la comunidad científica en los últimos años con el objetivo de incrementar la eficiencia energética en el ámbito considerado. En concreto, se han descrito y referido numerosas técnicas de compensación, interpolación, submuestreo y simplificación de la circuitería analógica. Como principal aportación original en este campo, se propone una técnica novedosa de calibración para compensación de offset y mismatch en el dominio analógico. Sobre la topología básica de un convertidor flash, se emplean técnicas de interpolación capacitiva para disminuir el número de amplificadores, mejorando las prestaciones en consumo sobre esquemas tradicionales. El esquema propuesto no usa capacidades a la entrada del convertidor, reduciendo así la carga en la misma y disminuyendo el consumo de los bloques anteriores. Además, la técnica presentada requiere de una única fase de reloj, disponiendo los amplificadores de más tiempo de trabajo en cada ciclo, resultando en una menor exigencia en sus prestaciones y ahorro en consumo. En el ámbito del diseño microelectrónico para aplicaciones en entornos de alta radiación, la principal aportación de esta Tesis Doctoral ha sido el desarrollo de un nuevo software de ayuda al diseño de circuitos robusto a radiación: AFTU (Analog Fault Tolerant University of Seville Debugging System). En el contexto considerado y en el marco de proyectos financiados por la Agencia Espacial Europea (Cosmic Vision, FTU2), se constata la necesidad de seguir una estricta metodología de evaluación y test de los circuitos diseñados para asegurar el correcto funcionamiento en entornos de alta radiación. El conocimiento de las partes más vulnerables a los efectos de la radiación es un punto crítico para el diseño tolerante a fallos de circuitos microelectrónicos en aplicaciones para el espacio, y se requiere una herramienta que permita un análisis rápido de vulnerabilidades en etapas tempranas de diseño. A lo largo de esta Tesis, se describe la arquitectura de la herramienta desarrollada, así como las principales características, parámetros de interés y ejemplos que permitan conocer su uso y potencialidad. Para evaluar y depurar el funcionamiento de la misma se ha evaluado la sensibilidad a SET de diferentes circuitos reales, empleando tanto diseños propios como ajenos analizados en colaboración con empresas. Esta evaluación ha permitido tanto depurar los errores detectados en el prototipo inicial, como definir nuevas heurísticas para el análisis de sensibilidad, así como incorporar paulatinamente nuevas tecnologías sobre las que poder realizar el análisis de sensibilidad ante SEE. Se incluyen en esta Tesis Doctoral algunos ejemplos de circuitos analizados, como muestra del potencial de la herramienta desarrollada

Network Electrophysiology Sensor-On-A- Chip

Electroencephalogram (EEG), Electrocardiogram (ECG), and Electromyogram (EMG) bio-potential signals are commonly recorded in clinical practice. Typically, patients are connected to a bulky and mains-powered instrument, which reduces their mobility and creates discomfort. This limits the acquisition time, prevents the continuous monitoring of patients, and can affect the diagnosis of illness. Therefore, there is a great demand for low-power, small-size, and ambulatory bio-potential signal acquisition systems. Recent work on instrumentation amplifier design for bio-potential signals can be broadly classified as using one or both of two popular techniques: In the first, an AC-coupled signal path with a MOS-Bipolar pseudo resistor is used to obtain a low-frequency cutoff that passes the signal of interest while rejecting large dc offsets. In the second, a chopper stabilization technique is designed to reduce 1/f noise at low frequencies. However, both of these existing techniques lack control of low-frequency cutoff. This thesis presents the design of a mixed- signal integrated circuit (IC) prototype to provide complete, programmable analog signal conditioning and analog-to-digital conversion of an electrophysiologic signal. A front-end amplifier is designed with low input referred noise of 1 uVrms, and common mode rejection ratio 102 dB. A novel second order sigma-delta analog- to-digital converter (ADC) with a feedback integrator from the sigma-delta output is presented to program the low-frequency cutoff, and to enable wide input common mode range of ¡Ãƒâ€œ0.3 V. The overall system is implemented in Jazz Semiconductor 0.18 um CMOS technology with power consumption 5.8 mW from ¡Ãƒâ€œ0.9V power supplies

Design and debugging of multi-step analog to digital converters

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has forced the A/D converter interface to reside on the same silicon in complex mixed-signal ICs containing mostly digital blocks for DSP and control. However, specifications of the converters in various applications emphasize high dynamic range and low spurious spectral performance. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons. Additionally, as CMOS integrated circuits are accomplishing unprecedented integration levels, potential problems associated with device scaling – the short-channel effects – are also looming large as technology strides into the deep-submicron regime. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. Practical realizations show the trend that to a first order, converter power is directly proportional to sampling rate. However, power dissipation required becomes nonlinear as the speed capabilities of a process technology are pushed to the limit. Pipeline and two-step/multi-step converters tend to be the most efficient at achieving a given resolution and sampling rate specification. This thesis is in a sense unique work as it covers the whole spectrum of design, test, debugging and calibration of multi-step A/D converters; it incorporates development of circuit techniques and algorithms to enhance the resolution and attainable sample rate of an A/D converter and to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover and compensate for the errors continuously. The power proficiency for high resolution of multi-step converter by combining parallelism and calibration and exploiting low-voltage circuit techniques is demonstrated with a 1.8 V, 12-bit, 80 MS/s, 100 mW analog to-digital converter fabricated in five-metal layers 0.18-µm CMOS process. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. Microscopic particles present in the manufacturing environment and slight variations in the parameters of manufacturing steps can all lead to the geometrical and electrical properties of an IC to deviate from those generated at the end of the design process. Those defects can cause various types of malfunctioning, depending on the IC topology and the nature of the defect. To relive the burden placed on IC design and manufacturing originated with ever-increasing costs associated with testing and debugging of complex mixed-signal electronic systems, several circuit techniques and algorithms are developed and incorporated in proposed ATPG, DfT and BIST methodologies. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. With the use of dedicated sensors, which exploit knowledge of the circuit structure and the specific defect mechanisms, the method described in this thesis facilitates early and fast identification of excessive process parameter variation effects. The expectation-maximization algorithm makes the estimation problem more tractable and also yields good estimates of the parameters for small sample sizes. To allow the test guidance with the information obtained through monitoring process variations implemented adjusted support vector machine classifier simultaneously minimize the empirical classification error and maximize the geometric margin. On a positive note, the use of digital enhancing calibration techniques reduces the need for expensive technologies with special fabrication steps. Indeed, the extra cost of digital processing is normally affordable as the use of submicron mixed signal technologies allows for efficient usage of silicon area even for relatively complex algorithms. Employed adaptive filtering algorithm for error estimation offers the small number of operations per iteration and does not require correlation function calculation nor matrix inversions. The presented foreground calibration algorithm does not need any dedicated test signal and does not require a part of the conversion time. It works continuously and with every signal applied to the A/D converter. The feasibility of the method for on-line and off-line debugging and calibration has been verified by experimental measurements from the silicon prototype fabricated in standard single poly, six metal 0.09-µm CMOS process

Potential and Challenges of Analog Reconfigurable Computation in Modern and Future CMOS

In this work, the feasibility of the floating-gate technology in analog computing platforms in a scaled down general-purpose CMOS technology is considered. When the technology is scaled down the performance of analog circuits tends to get worse because the process parameters are optimized for digital transistors and the scaling involves the reduction of supply voltages. Generally, the challenge in analog circuit design is that all salient design metrics such as power, area, bandwidth and accuracy are interrelated. Furthermore, poor flexibility, i.e. lack of reconfigurability, the reuse of IP etc., can be considered the most severe weakness of analog hardware. On this account, digital calibration schemes are often required for improved performance or yield enhancement, whereas high flexibility/reconfigurability can not be easily achieved. Here, it is discussed whether it is possible to work around these obstacles by using floating-gate transistors (FGTs), and analyze problems associated with the practical implementation. FGT technology is attractive because it is electrically programmable and also features a charge-based built-in non-volatile memory. Apart from being ideal for canceling the circuit non-idealities due to process variations, the FGTs can also be used as computational or adaptive elements in analog circuits. The nominal gate oxide thickness in the deep sub-micron (DSM) processes is too thin to support robust charge retention and consequently the FGT becomes leaky. In principle, non-leaky FGTs can be implemented in a scaled down process without any special masks by using “double”-oxide transistors intended for providing devices that operate with higher supply voltages than general purpose devices. However, in practice the technology scaling poses several challenges which are addressed in this thesis. To provide a sufficiently wide-ranging survey, six prototype chips with varying complexity were implemented in four different DSM process nodes and investigated from this perspective. The focus is on non-leaky FGTs, but the presented autozeroing floating-gate amplifier (AFGA) demonstrates that leaky FGTs may also find a use. The simplest test structures contain only a few transistors, whereas the most complex experimental chip is an implementation of a spiking neural network (SNN) which comprises thousands of active and passive devices. More precisely, it is a fully connected (256 FGT synapses) two-layer spiking neural network (SNN), where the adaptive properties of FGT are taken advantage of. A compact realization of Spike Timing Dependent Plasticity (STDP) within the SNN is one of the key contributions of this thesis. Finally, the considerations in this thesis extend beyond CMOS to emerging nanodevices. To this end, one promising emerging nanoscale circuit element - memristor - is reviewed and its applicability for analog processing is considered. Furthermore, it is discussed how the FGT technology can be used to prototype computation paradigms compatible with these emerging two-terminal nanoscale devices in a mature and widely available CMOS technology.Siirretty Doriast

Analysis and Design of High-Speed A/D Converters in SiGe Technology

Mixed-signal systems play a key role in modern communications and electronics. The quality of A/D and D/A conversions deeply affects what we see and what we hear in the real world video and radio. This dissertation deals with high-speed ADCs: a 5-bit 500-MSPS ADC and an 8-bit 2-GSPS ADC. These units can be applied in flat panel display, image enhancement and in high-speed data link. To achieve the state-of-the-art performance, we employed a 0.13-μm/2.5-V 210-GHz (unity-gain frequency) BiCMOS SiGe process for all the implementations. The circuit building blocks, such as the Track-and-Hold circuit (T/H) and the comparator, required by an ADC not only benefit from SiGe's superior ultra-high frequency properties but also by its power drive capability. The T/H described here achieved a dynamic performance of 8-bit accuracy at 2-GHz Nyquist rate with an input full scale range of 1 Vp-p. The T/H consumed 13 mW of power. The unique 4-in/2-out comparator was made of fully differential emitter couple pairs in order to operate at such a high frequency. Cascaded cross-coupled amplifier core was employed to reduce Miller effect and to avoid collector-emitter breakdown of the HBTs. We utilized the comparator interpolation technique between the preamplifer stages and the latches to reduce the total power dissipated by the comparator array. In addition, we developed an innovative D/A conversion and analog subtraction approach necessary for two-step conversion by using a bipolar pre-distortion technique. This innovation enabled us to decrease the design complexity in the subranging process of a two-step ADC. The 5-bit interpolating ADC operated at 2-GSPS achieved a differential nonlinearity (DNL) of 0.114 LSB and an integral nonlinearity (INL) of 0.076 LSB. The effective number of bits (ENOBs) are 4.3 bits at low frequency and 4.1 bits near Nyquist rate. The power dissipation was reduced more than half to 66.14 mW, with comparator interpolation. The 8-bit two-step interpolating ADC operated at 500-MSPS. It achieved a DNL of 0.33 LSB and an INL of 0.40 LSB with a power consumption of 172 mW. The ENOBs are 7.5 bits at low frequency and 6.9 bits near Nyquist rate