Efficient Sharing of Optical Resources in Low-Power Optical Networks-on-Chip

With the ever-growing core counts in modern computing systems, NoCs consume an increasing part of the power budget due to bandwidth and power density limitations of electrical interconnects. To maintain performance and power scaling, alternative technologies are required, with silicon photonics, sophisticated network designs are required to minimize static power overheads. In this paper, we propose Amon, a low-power ONoC that decreases number of μRings, wavelengths and path losses to reduce power consumption. Amom performs destination checking prior to data transmission on an underlying control network, allowing the sharing per-Watt by at least 23% (up to 70%), while reducing power without latency overheads on both synthetic and realistic applications. For aggressive optical technology parameters, Amom considerably outperforms all alternative NoCs in terms of power, outlining its increasing superiority as technology matures

High-Performance, Scalable Optical Network-On-Chip Architectures

The rapid advance of technology enables a large number of processing cores to be integrated into a single chip which is called a Chip Multiprocessor (CMP) or a Multiprocessor System-on-Chip (MPSoC) design. The on-chip interconnection network, which is the communication infrastructure for these processing cores, plays a central role in a many-core system. With the continuously increasing complexity of many-core systems, traditional metallic wired electronic networks-on-chip (NoC) became a bottleneck because of the unbearable latency in data transmission and extremely high energy consumption on chip. Optical networks-on-chip (ONoC) has been proposed as a promising alternative paradigm for electronic NoC with the benefits of optical signaling communication such as extremely high bandwidth, negligible latency, and low power consumption. This dissertation focus on the design of high-performance and scalable ONoC architectures and the contributions are highlighted as follow: 1. A micro-ring resonator (MRR)-based Generic Wavelength-routed Optical Router (GWOR) is proposed. A method for developing any sized GWOR is introduced. GWOR is a scalable non-blocking ONoC architecture with simple structure, low cost and high power efficiency compared to existing ONoC designs. 2. To expand the bandwidth and improve the fault tolerance of the GWOR, a redundant GWOR architecture is designed by cascading different type of GWORs into one network. 3. The redundant GWOR built with MRR-based comb switches is proposed. Comb switches can expand the bandwidth while keep the topology of GWOR unchanged by replacing the general MRRs with comb switches. 4. A butterfly fat tree (BFT)-based hybrid optoelectronic NoC (HONoC) architecture is developed in which GWORs are used for global communication and electronic routers are used for local communication. The proposed HONoC uses less numbers of electronic routers and links than its counterpart of electronic BFT-based NoC. It takes the advantages of GWOR in optical communication and BFT in non-uniform traffic communication and three-dimension (3D) implementation. 5. A cycle-accurate NoC simulator is developed to evaluate the performance of proposed HONoC architectures. It is a comprehensive platform that can simulate both electronic and optical NoCs. Different size HONoC architectures are evaluated in terms of throughput, latency and energy dissipation. Simulation results confirm that HONoC achieves good network performance with lower power consumption

CROSS-LAYER DESIGN, OPTIMIZATION AND PROTOTYPING OF NoCs FOR THE NEXT GENERATION OF HOMOGENEOUS MANY-CORE SYSTEMS

This thesis provides a whole set of design methods to enable and manage the runtime heterogeneity of features-rich industry-ready Tile-Based Networkon- Chips at different abstraction layers (Architecture Design, Network Assembling, Testing of NoC, Runtime Operation). The key idea is to maintain the functionalities of the original layers, and to improve the performance of architectures by allowing, joint optimization and layer coordinations. In general purpose systems, we address the microarchitectural challenges by codesigning and co-optimizing feature-rich architectures. In application-specific NoCs, we emphasize the event notification, so that the platform is continuously under control. At the network assembly level, this thesis proposes a Hold Time Robustness technique, to tackle the hold time issue in synchronous NoCs. At the network architectural level, the choice of a suitable synchronization paradigm requires a boost of synthesis flow as well as the coexistence with the DVFS. On one hand this implies the coexistence of mesochronous synchronizers in the network with dual-clock FIFOs at network boundaries. On the other hand, dual-clock FIFOs may be placed across inter-switch links hence removing the need for mesochronous synchronizers. This thesis will study the implications of the above approaches both on the design flow and on the performance and power quality metrics of the network. Once the manycore system is composed together, the issue of testing it arises. This thesis takes on this challenge and engineers various testing infrastructures. At the upper abstraction layer, the thesis addresses the issue of managing the fully operational system and proposes a congestion management technique named HACS. Moreover, some of the ideas of this thesis will undergo an FPGA prototyping. Finally, we provide some features for emerging technology by characterizing the power consumption of Optical NoC Interfaces

High Efficiency Silicon Photonic Interconnects

Silicon photonic has provided an opportunity to enhance future processor speed by replacing copper interconnects with an on chip optical network. Although photonics are supposed to be efficient in terms of power consumption, speed, and bandwidth, the existing silicon photonic technologies involve problems limiting their efficiency. Examples of limitations to efficiency are transmission loss, coupling loss, modulation speed limited by electro-optical effect, large amount of energy required for thermal control of devices, and the bandwidth limit of existing optical routers. The objective of this dissertation is to investigate novel materials and methods to enhance the efficiency of silicon photonic devices. The first part of this dissertation covers the background, theory and design of on chip optical interconnects, specifically silicon photonic interconnects. The second part describes the work done to build a 300mm silicon photonic library, including its process flow, comprised of basic elements like electro-optical modulators, germanium detectors, Wavelength Division Multiplexing (WDM) interconnects, and a high efficiency grating coupler. The third part shows the works done to increase the efficiency of silicon photonic modulators, unitizing the χ(3) nonlinear effect of silicon nanocrystals to make DC Kerr effect electro-optical modulator, combining silicon with lithium niobate to make χ(2) electro-optical modulators on silicon, and increasing the efficiency of thermal control by incorporating micro-oven structures in electro-optical modulators. The fourth part introduces work done on dynamic optical interconnects including a broadband optical router, single photon level adiabatic wavelength conversion, and optical signal delay. The final part summarizes the work and talks about future development