Improve Performance of Adaptive Multi-Modulus Frequency Divider by Pulse Triggered Flip Flop

A divider of frequency with minimal power & greater speed with multi modulus is elaborated along design of a PLL. In this document by making use of a ff initiated by a pulse is plowed by which a definite divider with 2 levels can improvise the frequency of function & deduce decadence of power. A constituent which is adaptive s formulated to be retained in a divider with great mode of saving in power. The frequency of a defined divider with 2 levels in accordance to CMOS of 130 nm process may attain 4 GHz. The basic decadence f power is division by 49 mode at 63 uW with frequency of 1 GHz or 156uW at 4 GHz. In a contrast of the counter of Johnson FD, frequency of a divider with 2 levels is improvised & so the proportion of optimization of power

Cumulative index to NASA Tech Briefs, 1970-1975

Tech briefs of technology derived from the research and development activities of the National Aeronautics and Space Administration are presented. Abstracts and indexes of subject, personal author, originating center, and tech brief number for the 1970-1975 tech briefs are presented