Performance issues for iterative solvers in device simulation

Due to memory limitations, iterative methods have become the method of choice for large scale semiconductor device simulation. However, it is well known that these methods still suffer from reliability problems. The linear systems which appear in numerical simulation of semiconductor devices are notoriously ill-conditioned. In order to produce robust algorithms for practical problems, careful attention must be given to many implementation issues. This paper concentrates on strategies for developing robust preconditioners. In addition, effective data structures and convergence check issues are also discussed. These algorithms are compared with a standard direct sparse matrix solver on a variety of problems

Theoretical and practical aspects of parallel numerical algorithms for initial value problems, with applications

Includes bibliographical references (p. 80-82).Supported by IBM Corp., and by a AEA/Dynatech faculty development fellowship. Supported by the Defense Advanced Research Projects Agency, under the Office of Naval Research. N00014-91-J-1698 Supported by a National Science Foundation. MIP-88-14612Andrew Lumsdaine

A class of linear solvers based on multilevel and supernodal factorization

De oplossing van grote en schaarse lineaire systemen is een kritieke component van moderne wetenschap en technische simulaties. Iteratieve methoden, namelijk de klasse van moderne Krylov-subruimtemethoden, worden vaak gebruikt om grootschalige lineaire systemen op te lossen. Om de robuustheid en de convergentiesnelheid van de iteratieve methoden te verbeteren, worden preconditioneringstechnieken vaak beschouwd als cruciale componenten van de lineaire systeemoplossing. In dit proefschrift wordt een klasse van algebraïsche multilevel oplossers gepresenteerd voor het conditioneren van algemene lineaire systeemvergelijkingen die voortkomen uit computationele wetenschap en technische toepassingen. Ze kunnen spaarzame patronen produceren en geheugenkosten besparen door recursieve combinatorische algoritmen toe te passen. Robuustheid wordt verbeterd door de factorisatie te combineren met recent ontwikkelde overlappende en compressiestrategieën en door efficiënte lokale oplossers te gebruiken. We hebben de goede prestaties van de voorgestelde strategieën aangetoond met numerieke experimenten op realistische matrixproblemen, ook in vergelijking met enkele van de meest populaire algebraïsche preconditioners die tegenwoordig worden gebruikt

Algorithms for Analysis of Nonlinear High-Frequency Circuits

The most efficient simulation solvers use composite procedures that adaptively rearrange computation algorithms to maximize simulation performance. Fast and stable processing optimized for given simulation problem is essential for any modern simulator. It is characteristic for electronic circuit analysis that complexity of simulation is affected by circuit size and used device models. Implementation of electronic device models in program SPICE uses traditional implementation allowing fast computation but further modification of model can be questionable. The first fundamental thesis aim is scalability of the simulation based on the adaptive internal solver composing different algorithms according to properties of simulation problem to maximize simulation performance. In a case of the small circuit as faster solution prove simple, straightforward methods that utilize arithmetic operations without unnecessary condition jumping and memory rearrangements that can not be effectively optimized by a compiler. The limit of small size simulation problems is related to computation machine capabilities. The present day PC sets this limit to fifty independent voltage nodes where inefficiency of calculation procedure does not play any role in overall processor performance. The scalable solver must also be able to handle correctly simulation of large-scale circuits that requires entirely different approach apart to standard size circuits. The unique properties of simulation of the electronic circuits that played until this time only the minor role suddenly gain on significance for circuits with several thousand voltage nodes. In those particular cases, iterative algorithms based on Krylov subspace methods provide better results from the aspect of performance than standard direct methods. This thesis also proposes unique techniques of indexation of the large-scale sparse matrix system. The primary purpose is to reduce memory requirements for storing sparse matrices during simulation computation. The second fundamental thesis aim is automatic adaptivity of device models definition respecting current simulation state and settings. This principle is denoted as Functional Chaining mechanism that is based on the principle of the automatic self-modifying procedure utilizing state-of-the-art functional computation layer during the simulation process. It can significantly improve mapping performance of circuit variables to device models; it also allows autonomous redefinition of simulation algorithms during analysis with an intention to reduce computation time. The core idea is based on utilization of programming principles related to functional programming languages. It is also presents possibilites of reimplementation to the modern object-oriented languages. The third fundamental thesis aim focuses on simulation accuracy and reliability. Arbitrary precision variable types can directly lead to increased simulation accuracy but on the other hand; they can significantly decrease simulation performance. In last chapters, there are several algorithms provided with the claim to provide better simulation accuracy and suppress computation errors of floating point data types.Katedra radioelektronik

SCALABLE INTEGRATED CIRCUIT SIMULATION ALGORITHMS FOR ENERGY-EFFICIENT TERAFLOP HETEROGENEOUS PARALLEL COMPUTING PLATFORMS

Integrated circuit technology has gone through several decades of aggressive scaling.It is increasingly challenging to analyze growing design complexity. Post-layout SPICE simulation can be computationally prohibitive due to the huge amount of parasitic elements, which can easily boost the computation and memory cost. As the decrease in device size, the circuits become more vulnerable to process variations. Designers need to statistically simulate the probability that a circuit does not meet the performance metric, which requires millions times of simulations to capture rare failure events. Recent, multiprocessors with heterogeneous architecture have emerged as mainstream computing platforms. The heterogeneous computing platform can achieve highthroughput energy efficient computing. However, the application of such platform is not trivial and needs to reinvent existing algorithms to fully utilize the computing resources. This dissertation presents several new algorithms to address those aforementioned two significant and challenging issues on the heterogeneous platform. Harmonic Balance (HB) analysis is essential for efficient verification of large postlayout RF and microwave integrated circuits (ICs). However, existing methods either suffer from excessively long simulation time and prohibitively large memory consumption or exhibit poor stability. This dissertation introduces a novel transient-simulation guided graph sparsification technique, as well as an efficient runtime performance modeling approach tailored for heterogeneous manycore CPU-GPU computing system to build nearly-optimal subgraph preconditioners that can lead to minimum HB simulation runtime. Additionally, we propose a novel heterogeneous parallel sparse block matrix algorithm by taking advantages of the structure of HB Jacobian matrices as well as GPU’s streaming multiprocessors to achieve optimal workload balancing during the preconditioning phase of HB analysis. We also show how the proposed preconditioned iterative algorithm can efficiently adapt to heterogeneous computing systems with different CPU and GPU computing capabilities. Extensive experimental results show that our HB solver can achieve up to 20X speedups and 5X memory reduction when compared with the state-of-the-art direct solver highly optimized for twelve-core CPUs. In nowadays variation-aware IC designs, cell characterizations and SRAM memory yield analysis require many thousands or even millions of repeated SPICE simulations for relatively small nonlinear circuits. In this dissertation, for the first time, we present a massively parallel SPICE simulator on GPU, TinySPICE, for efficiently analyzing small nonlinear circuits. TinySPICE integrates a highly-optimized shared-memory based matrix solver and fast parametric three-dimensional (3D) LUTs based device evaluation method. A novel circuit clustering method is also proposed to improve the stability and efficiency of the matrix solver. Compared with CPU-based SPICE simulator, TinySPICE achieves up to 264X speedups for parametric SRAM yield analysis without loss of accuracy

Application of HPC in eddy current electromagnetic problem solution

As engineering problems are becoming more and more advanced, the size of an average model solved by partial differential equations is rapidly growing and, in order to keep simulation times within reasonable bounds, both faster computers and more efficient software implementations are needed. In the first part of this thesis, the full potential of simulation software has been exploited through high performance parallel computing techniques. In particular, the simulation of induction heating processes is accomplished within reasonable solution times, by implementing different parallel direct solvers for large sparse linear system, in the solution process of a commercial software. The performance of such library on shared memory systems has been remarkably improved by implementing a multithreaded version of MUMPS (MUltifrontal Massively Parallel Solver) library, which have been tested on benchmark matrices arising from typical induction heating process simulations. A new multithreading approach and a low rank approximation technique have been implemented and developed by MUMPS team in Lyon and Toulouse. In the context of a collaboration between MUMPS team and DII-University of Padova, a preliminary version of such functionalities could be tested on induction heating benchmark problems, and a substantial reduction of the computational cost and memory requirements could be achieved. In the second part of this thesis, some examples of design methodology by virtual prototyping have been described. Complex multiphysics simulations involving electromagnetic, circuital, thermal and mechanical problems have been performed by exploiting parallel solvers, as developed in the first part of this thesis. Finally, multiobjective stochastic optimization algorithms have been applied to multiphysics 3D model simulations in search of a set of improved induction heating device configurations

Seventh Copper Mountain Conference on Multigrid Methods

The Seventh Copper Mountain Conference on Multigrid Methods was held on 2-7 Apr. 1995 at Copper Mountain, Colorado. This book is a collection of many of the papers presented at the conference and so represents the conference proceedings. NASA Langley graciously provided printing of this document so that all of the papers could be presented in a single forum. Each paper was reviewed by a member of the conference organizing committee under the coordination of the editors. The multigrid discipline continues to expand and mature, as is evident from these proceedings. The vibrancy in this field is amply expressed in these important papers, and the collection shows its rapid trend to further diversity and depth

Preconditioners for iterative solutions of large-scale linear systems arising from Biot's consolidation equations

Ph.DDOCTOR OF PHILOSOPH

CMVSIM user's guide

Includes bibliographical references (p. 29-30).Supported by the National Science Foundation. MIP 91-17724A. Lumsdaine, M. Silveira, J. White