Explicit constructions of Type-II QC LDPC codes with girth at least 6

Type-II quasi-cyclic (QC) LDPC codes are constructed from combinations of weight-0, weight-1 and weight-2 circulant matrices. The structure of cycles of length 2n are investigated, and necessary and sufficient conditions for a type-II QC LDPC parity check matrix H to have girth at least 2(n+1) are given. An explicit construction of type-II codes which guarantees girth at least 6 is presented. A necessary and sufficient condition for a QC matrix with one or more rows of circulants, to be fullrank is derived

Spherical and Hyperbolic Toric Topology-Based Codes On Graph Embedding for Ising MRF Models: Classical and Quantum Topology Machine Learning

The paper introduces the application of information geometry to describe the ground states of Ising models by utilizing parity-check matrices of cyclic and quasi-cyclic codes on toric and spherical topologies. The approach establishes a connection between machine learning and error-correcting coding. This proposed approach has implications for the development of new embedding methods based on trapping sets. Statistical physics and number geometry applied for optimize error-correcting codes, leading to these embedding and sparse factorization methods. The paper establishes a direct connection between DNN architecture and error-correcting coding by demonstrating how state-of-the-art architectures (ChordMixer, Mega, Mega-chunk, CDIL, ...) from the long-range arena can be equivalent to of block and convolutional LDPC codes (Cage-graph, Repeat Accumulate). QC codes correspond to certain types of chemical elements, with the carbon element being represented by the mixed automorphism Shu-Lin-Fossorier QC-LDPC code. The connections between Belief Propagation and the Permanent, Bethe-Permanent, Nishimori Temperature, and Bethe-Hessian Matrix are elaborated upon in detail. The Quantum Approximate Optimization Algorithm (QAOA) used in the Sherrington-Kirkpatrick Ising model can be seen as analogous to the back-propagation loss function landscape in training DNNs. This similarity creates a comparable problem with TS pseudo-codeword, resembling the belief propagation method. Additionally, the layer depth in QAOA correlates to the number of decoding belief propagation iterations in the Wiberg decoding tree. Overall, this work has the potential to advance multiple fields, from Information Theory, DNN architecture design (sparse and structured prior graph topology), efficient hardware design for Quantum and Classical DPU/TPU (graph, quantize and shift register architect.) to Materials Science and beyond.Comment: 71 pages, 42 Figures, 1 Table, 1 Appendix. arXiv admin note: text overlap with arXiv:2109.08184 by other author

LEDAkem: a post-quantum key encapsulation mechanism based on QC-LDPC codes

This work presents a new code-based key encapsulation mechanism (KEM) called LEDAkem. It is built on the Niederreiter cryptosystem and relies on quasi-cyclic low-density parity-check codes as secret codes, providing high decoding speeds and compact keypairs. LEDAkem uses ephemeral keys to foil known statistical attacks, and takes advantage of a new decoding algorithm that provides faster decoding than the classical bit-flipping decoder commonly adopted in this kind of systems. The main attacks against LEDAkem are investigated, taking into account quantum speedups. Some instances of LEDAkem are designed to achieve different security levels against classical and quantum computers. Some performance figures obtained through an efficient C99 implementation of LEDAkem are provided.Comment: 21 pages, 3 table

FPGA Implementation of encoders for CCSDS Low-Density Parity-Check (LDPC) codes.

Η παρούσα διπλωματική εργασία παρουσιάζει την υλοποίηση με τεχνολογία FPGA αλγορίθμων κωδικοποίησης καναλιού που έχουν προτυποποιηθεί από τον οργανισμό CCSDS για χρήση σε διαστημικές επικοινωνίες. Ο CCSDS προτείνει δύο κατηγορίες κωδίκων για εφαρμογές τηλεμετρίας: μία για επικοινωνίες στο εγγύς (near-earth) διάστημα (π.χ. δορυφορικές επικοινωνίες) και άλλη μια για επικοινωνίες βαθέος διαστήματος (deep-space), με χαρακτηριστικά η κάθε μία βελτιστοποιημένα ως προς το πεδίο εφαρμογής τους. Και στις δύο περιπτώσεις, οι κώδικες είναι γραμμικοί μπλοκ κώδικες με μεγάλο μέγεθος μπλοκ και πίνακα ισοτιμίας με χαμηλή πυκνότητα (LDPC). Στην παρούσα εργασία, γίνεται εκμετάλλευση της δομής των πινάκων-γεννητόρων των κωδίκων deep-space προκειμένου να μεγιστοποιηθεί η απόδοση. Προκύπτουν δύο ειδών παραλληλίες στη δομή των εν λόγω πινάκων, η ταυτόχρονη αξιοποίηση των οποίων οδηγεί σε βελτίωση των επιδόσεων με ελαχιστοποίηση των καταναλισκόμενων πόρων. Αντίστοιχα στην περίπτωση του κώδικα near-earth, περιγράφεται μια αποδοτική μέθοδος στη σχεδίαση των επί μέρους οντοτήτων του κυκλώματος που βελτιστοποιεί την αξιοποίηση των πόρων, σε σχέση με γνωστές λύσεις. Η περιγραφή των κωδικοποιητών σε VHDL επαληθεύεται ως προς την ορθή της σχεδίαση με προσομοιώσεις για όλες τις υποστηριζόμενες περιπτώσεις, όπου απαιτείται η μέγιστη κάλυψη κώδικα (code coverage). Τέλος, το σχέδιο επαλήθευσης περιλαμβάνει την επίδειξη λειτουργίας σε ένα ενσωματωμένο σύστημα υλοποιημένο στην κάρτα XUPV505-LX110T, όπου καταγράφονται και οι πραγματικές επιδόσεις του συστήματος, όπου βρίσκονται στην περιοχή των μερικών Gbps. Η παρούσα υλοποίηση προκύπτει ότι είναι η ταχύτερη για την συγκεκριμένη οικογένεια LDPC κωδικών, που έχει επιτευχθεί μέχρι σήμερα.The FPGA implementation of LDPC encoders for channel codes standardized by CCSDS for space communication applications is described in this work. CCSDS suggests two classes of channel codes for telemetry applications: one for near-earth and another for deep-space communications, each one optimized for the demands of the specific field. In both cases, the specification concerns linear block codes with large block size and sparse generator matrices. Regarding near-earth codes, the specification describes a Euclidean geometry based (8160,7136) LDPC code at rate 7/8, while in the deep-space case, 9 codes are defined which are the combination of thee block lengths (1024,4096,16384 bits) with three rates (½, 2/3, 4/5), sharing a common mathematical description. This fact enables the VHDL description of a common encoder for all of them. The generator matrices of these codes possess considerable structure which facilitates implementation. Concerning deep-space codes generator matrices, parallelism extends over two dimensions, which can be exploited concurrently to optimize timing performance and at the same time minimize resource utilization. The price to be paid however is increased latency, which can be mitigated by the pipelined operation of the output interface. VHDL description of the encoder is generic, allowing the easy modification of the code parameters (block size, rate), the amount of parallelism in each dimension and the input-output bus width, leading to different performance-latency balances. Also in the case of the near-earth code, an efficient design of the encoder's sub-entities is described, leading to resources utilization optimizations, compared to existing implementations. The encoder in this case is designed for 16-bit input-output bus. All described encoders input-output is performed on AMBA AXI-4 Stream compliant interfaces, facilitating their integration in an embedded system's design and communication with standard FIFO interfaces. The encoders' operation is optimal in that an uninterrupted flow of data is provided on the output interface, without idle cycles. The only exception is the near-earth encoder for which just one idle cycle every 513 is inserted. The correctness of the VHDL description's is validated by functional simulation for all supported cases, where 100% code coverage is demanded. The verification plan includes also the demonstration of real-time operation of the encoders in an integrated system implemented on a XUPV505-LX110T development board, where the actual performance of the encoders is recorded and lies in the multi-Gbps range. Finally, the proposed encoders are shown to be the fastest stream-oriented implementations for the specified family of LDPC codes, with minimal resource utilization

FPGE implementation of LDPC codes

Low density parity check LDPC Code is a type of Block Error Correction code discovered and performance very close to Shanon’s limit .Good error correcting performance enables reliable communication. Since its discovery by Gallagar there is more research going on for its efficient construction and implementation. Though there is no unique method for constructing LDPC codes. Implementation of LDPC Code is done by taking different factors in to consideration such as error rate, parallelism of decoder, ease in implementation etc. This thesis is about FPGA implementation of LDPC codes and their performance evaluation. Protograph codes were introduced and analyzed by NASA's Jet Propulsion Laboratory in the early years of this century. Part of this thesis continues that work, investigating the decoding of specific protograph codes and extending existing tools for analyzing codes to protograph codes In this thesis I have taken the performance of LDPC coded BPSK modulated signal which is transmitted through AWGN channel and the performance is tested using MATLAB Simulation

비신뢰 경로 검색 기법을 이용한 저밀도 패리티 체크 부호를 위한 저복잡도 복호 기법 연구

학위논문 (박사)-- 서울대학교 대학원 공과대학 전기·컴퓨터공학부, 2017. 8. 노종선.This dissertation contains the following contributions on the low-complexity decoding schemes of LDPC codes. Two-stage decoding scheme for LDPC codes – A new stopping criterion for LDPC codes – A new decoding scheme for LDPC codes with unreliable path search Parallel unreliable path search algorithm Analysis of two-stage decoding schemes – Validity and complexity analysis First, a new two-stage decoding scheme for low-density parity check (LDPC) codes to lower the error-floor is proposed. The proposed decoding scheme consists of the conventional belief propagation (BP) decoding algorithm as the first-stage decoding and the re-decodings with manipulated log-likelihood ratios (LLRs) of variable nodes as the second-stage decoding. In the first-stage decoding, an early stopping criterion is proposed for early detection of decoding failure and the candidate set of the variable nodes is determined, which can be partly included in the small trapping sets. In the second-stage decoding, the scores of the variable nodes in the candidate set are computed by the proposed unreliable path search algorithm and the variable nodes are sorted in ascending order by their scores for the re-decoding trials. Each re-decoding trial is performed by BP decoding algorithm with manipulated LLR of a selected variable node in the candidate set one at a time with the second early stopping criterion. Secondly, the parallel unreliable path search algorithm is proposed for practical application to the proposed unreliable path search algorithm. In order to reduce the decoding delay and computational complexity, an efficient method for the search algorithm based on the parallel message-passing algorithm in the LDPC decoding is proposed. The parallel unreliable path search algorithm significantly reduces the additional complexity without extra hardware requirements. Finally, the validity and the complexity analysis of the proposed unreliable path search algorithm is presented. The proposed algorithm effectively finds the variable nodes in small trapping sets much more faster than the previous random selection method. Also, it is verified that the additional complexity of the parallel unreliable path search algorithm is less than that of one iteration of iterative decoders.Abstract i Contents iii List of Tables v List of Figures vi 1 Introduction 1 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Overview of Dissertation . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Overview of LDPC Codes 9 2.1 Basic Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 Decoding of LDPC Codes . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 Analysis of LDPC Codes . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.1 Density Evolution . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.2 Mean Evolution . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4 Quasi-Cyclic LDPC Codes . . . . . . . . . . . . . . . . . . . . . . . 19 2.5 Error-Floor and Trapping Sets . . . . . . . . . . . . . . . . . . . . . 21 3 A New Two-Stage Decoding Scheme with Unreliable Path Search 23 3.1 Overview of The Proposed Two-Stage Decoding Scheme . . . . . . . 26 3.2 First-Stage Decoding with the First Early Stopping Criterion . . . . . 27 3.3 Second-Stage Decoding with Unreliable Path Search Algorithm . . . 36 3.3.1 Scoring by Unreliable Path Search Algorithm . . . . . . . . . 37 3.3.2 LLR Manipulation and Re-decoding with the Second Early Stopping Criterion . . . . . . . . . . . . . . . . . . . . . . . 42 4 Parallel Unreliable Path Search Algorithm 44 4.1 Description of Parallel Unreliable Path Search Algorithm . . . . . . . 44 4.2 Scoring by Parallel Unreliable Path Search Algorithm . . . . . . . . . 48 5 Analysis of the Unreliable Path Search Algorithm 51 5.1 Validity of the Unreliable Path Search Algorithm . . . . . . . . . . . 51 5.2 Complexity Analysis of the Unreliable Path Search Algorithm . . . . 56 6 Simulation Results 59 7 Conclusions 65 Abstract (In Korean) 73Docto