A Massively Parallel 2D Rectangle Placement Method

Layout design is a frequently occurring process that oftencombines human and computer reasoning. Because of the combinatorialnature of the problem, solving even a small size input involves searchinga prohibitively large state space. An algorithm PEMS (Pseudo-exhaustiveEdge Minimizing Search) is proposed for approximating a 2D rectanglepacking variant of the problem. The proposed method is inspiredby MERA (Minimum Enclosing of Rectangle Area) [1] and MEGA(Minimum Enclosing Under Gravitational Attraction) [2], yet produceshigher quality solutions, in terms of final space utilization. To addressthe performance cost, a CUDA based acceleration algorithm is developedwith significant speedup

Timing-Driven Macro Placement

Placement is an important step in the process of finding physical layouts for electronic computer chips. The basic task during placement is to arrange the building blocks of the chip, the circuits, disjointly within a given chip area. Furthermore, such positions should result in short circuit interconnections which can be routed easily and which ensure all signals arrive in time. This dissertation mostly focuses on macros, the largest circuits on a chip. In order to optimize timing characteristics during macro placement, we propose a new optimistic timing model based on geometric distance constraints. This model can be computed and evaluated efficiently in order to predict timing traits accurately in practice. Packing rectangles disjointly remains strongly NP-hard under slack maximization in our timing model. Despite of this we develop an exact, linear time algorithm for special cases. The proposed timing model is incorporated into BonnMacro, the macro placement component of the BonnTools physical design optimization suite developed at the Research Institute for Discrete Mathematics. Using efficient formulations as mixed-integer programs we can legalize macros locally while optimizing timing. This results in the first timing-aware macro placement tool. In addition, we provide multiple enhancements for the partitioning-based standard circuit placement algorithm BonnPlace. We find a model of partitioning as minimum-cost flow problem that is provably as small as possible using which we can avoid running time intensive instances. Moreover we propose the new global placement flow Self-Stabilizing BonnPlace. This approach combines BonnPlace with a force-directed placement framework. It provides the flexibility to optimize the two involved objectives, routability and timing, directly during placement. The performance of our placement tools is confirmed on a large variety of academic benchmarks as well as real-world designs provided by our industrial partner IBM. We reduce running time of partitioning significantly and demonstrate that Self-Stabilizing BonnPlace finds easily routable placements for challenging designs – even when simultaneously optimizing timing objectives. BonnMacro and Self-Stabilizing BonnPlace can be combined to the first timing-driven mixed-size placement flow. This combination often finds placements with competitive timing traits and even outperforms solutions that have been determined manually by experienced designers

A Polyhedral Study of Mixed 0-1 Set

We consider a variant of the well-known single node fixed charge network flow set with constant capacities. This set arises from the relaxation of more general mixed integer sets such as lot-sizing problems with multiple suppliers. We provide a complete polyhedral characterization of the convex hull of the given set

Computation with Curved Shapes: Towards Freeform Shape Generation in Design

Shape computations are a formal representation that specify particular aspects of the design process with reference to form. They are defined according to shape grammars, where manipulations of pictorial representations of designs are formalised by shapes and rules applied to those shapes. They have frequently been applied in architecture in order to formalise the stylistic properties of a given corpus of designs, and also to generate new designs within those styles. However, applications in more general design fields have been limited. This is largely due to the initial definitions of the shape grammar formalism which are restricted to rectilinear shapes composed of lines, planes or solids. In architecture such shapes are common but in many design fields, for example industrial design, shapes of a more freeform nature are prevalent. Accordingly, the research described in this thesis is concerned with extending the applicability of the shape grammar formalism such that it enables computation with freeform shapes. Shape computations utilise rules in order to manipulate subshapes of a design within formal algebras. These algebras are specified according to embedding properties and have previously been defined for rectilinear shapes. In this thesis the embedding properties of freeform shapes are explored and the algebras are extended in order to formalise computations with such shapes. Based on these algebras, shape operations are specified and algorithms are introduced that enable the application of rules to shapes composed of freeform B´ezier curves. Implementation of the algorithms enables the application of shape grammars to shapes of a more freeform nature than was previously possible. Within this thesis shape grammar implementations are introduced in order to explore both theoretical issues that arise when considering computation with freeform shapes and practical issues concerning the application of shape computation as a model for design and as a mode for generating freeform shapes