Nanoscale strain characterisation of modern microelectronic devices

PhD ThesisSources of stress and strain in modern microelectronics can be either beneficial to the electrical performance or detrimental to the mechanical integrity and ultimately lifetime of the device. Strain engineering is commonplace in state-of-the-art device fabrication as a means to boost performance in the face of device scaling limitation. The strain present in the device is directly related to the improvement factor and as such precise measurements and good understanding are of utmost importance due to the many thermal processing steps that can induce or cause relaxation of the strain. Front-end-of-line (FEOL) strain characterisation is becoming increasingly challenging due to the small volumes of material and nanoscale feature sizes being analysed. In this work, an extensive survey of strain characterisation techniques was undertaken. Narrow sSOI stripes were profiled using conventional Raman spectroscopy. Unlike with previous studies, it was shown that it is possible to achieve nanoscale measurements using current techniques. This study was supported by ANSYS FE simulation. The review of the literature briefly investigates the possibility of EBSD as a strain measurement tool. It is possible to calculate not just an absolute strain value as achievable with Raman spectroscopy, but the strain tensor. However, this is a difficult and complex process and not necessary for use in industry. This study proposes the possibility of a more simple method that would provide a good calibration technique to confirm Raman measurements. SERS and TERS are explored in detail as the most promising techniques when dealing with device scaling. Currently, SERS is a destructive technique not suitable for use in a highly cost driven industry such as semiconductor manufacturing. While it theoretically gives improved surface selectivity over conventional Raman spectroscopy, there is no improvement to the xy spatial resolution. With Si and SiGe samples, this study concludes there is also often no surface selectivity with either technique and the mechanisms behind the enhancement are not understood to the point of being able to implement the techniques in a process line. However, where a non-destructive technique is desired, outlined in this study is a method of achieving the SERS effect without sacrificing the sample. Aggressive scaling has forced the dimensions of the interconnecting wires that give the devices functionality to the deep submicron range. Copper, Cu has been introduced as a replacement to the traditionally used aluminium, Al because of its superior electrical and mechanical properties and scalability. However, as these wires begin to approach the dimensions of thin foils, the microtexture of the wires becomes significantly different from their bulk counterparts. This can affect the mechanical integrity of the interconnects and this has an impact on the reliability of the device. Failure mechanisms such as blistering, cracking and peeling caused by stress and strain are not uncommon and traditional methods of characterising residual stress in the thin films is no longer applicable to these narrow wires. The mechanical properties and microtexture of thin copper films annealed at temperatures comparative to those found in device manufacturing were characterised in some detail. EBSD was used to determine the grain size and structure of the films before nanoindentation confirmed properties such as hardness and elastic modulus. These results pave the way for investigation of strain applied along deep-submicron interconnects to lead to further understanding of what causes failure mechanisms from interconnecting wires

Electromigration behavior and reliability of bamboo Al(Cu) interconnects for integrated circuits

Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 1999.Includes bibliographical references (leaves 103-108).by V.T. Srikar.Ph.D

Electromigration time-to-failure analysis using a lumped element model

This thesis presents a theoretical and computer simulation of electromigration behaviour in the Integrated Circuit (IC) interconnection, with a particular emphasis on the analysis of the time-to-failure (TTF) produced through the Lumped Element model. The current and most accepted physical model for electromigration is the Stress Evolution Model which forms the basis for the development of the current Lumped Element Model. For early failures, and ignoring transport through the grain bulk, the problem reduces to that of solving the equations for stress evolution equation on the complex grain boundary networks which make the cluster sections of the near-bamboo interconnect. The present research attempts to show that the stress evolution in a grain boundary cluster network mimics the time development of the voltage on an equivalent, lumped CRC electrical network. [Continues.

A CAD tool for the prediction of VLSI interconnect reliability.

Thesis (Ph.D.)-University of Natal, Durban, 1988.This thesis proposes a new approach to the design of reliable VLSI interconnects, based on predictive failure models embedded in a software tool for reliability analysis. A method for predicting the failure rate of complex integrated circuit interconnects subject to electromigration, is presented. This method is based on the principle of fracturing an interconnect pattern into a number of statistically independent conductor segments. Five commonly-occurring segment types are identified: straight runs, steps resulting from a discontinuity in the wafer surface, contact windows, vias and bonding pads. The relationship between median time-to-failure (Mtf) of each segment and physical dimensions, temperature and current density are determined. This model includes the effect of time-varying current density. The standard deviation of lifetime is also determined as a function of dimensions. A· minimum order statistical method is used to compute the failure rate of the interconnect system. This method, which is applicable to current densities below 106 AI cm2 , combines mask layout and simulation data from the design data base with process data to calculate failure rates. A suite of software tools called Reliant (RELIability Analyzer for iNTerconnects) which implements the algorithms described above, is presented. Reliant fractures a conductor pattern into segments and extracts electrical equivalent circuits for each segment. The equivalent circuits are used in conjunction with a modified version of the SPICE circuit simulator to determine the currents in all segments and to compute reliability. An interface to a data base query system provides the capability to access reliability data interactively. The performance of Reliant is evaluated, based on two CMOS standard cell layouts. Test structures for the calibration of the reliability models are provided. Reliant is suitable for the analysis of leaf cells containing a few hundred transistors. For MOS VLSI circuits, an alternative approach based on the use of an event-driven switch-level simulator is presented

Electrophoretically deposited copper manganese spinel protective coatings on metallic interconnects for prevention of Cr-poisoning in solid oxide fuel cells

Metallic interconnects in intermediate temperature solid oxide fuel cells (IT-SOFC) stacks form Cr2O3 scales on their surface. Such oxide scales can be further oxidized to Cr6+ containing gaseous species that migrate and deposit at the cathode triple phase boundaries, causing significant degradation in the performance of the SOFCs. This phenomenon is termed as ‘Cr-poisoning’. A solution to this problem is the application of coatings on the interconnects that act as a diffusion barrier to Cr migration. Two different Cu/Mn spinel compositions, Cu1.3Mn1.7O4 and CuMn1.8O4, were studied as coating materials. Dense coatings were deposited on both flat plates and meshes by electrophoretic deposition (EPD) followed by subsequent thermo-mechanical or thermal densification steps. At room temperature, Cu1.3Mn1.7O4 coatings were found to have a mixture of CuO and spinel phases, while CuMn1.8O4 coatings were found to have a mixture of Mn3O4 and spinel phases. However, CuMn1.8O4 is a pure spinel phase between 750 °C and 850 °C. After densification processing and high temperature oxidation, a Cr2O3 layer was formed at the coating/alloy interface, which partially reacted with the spinel coatings to form a dense cubic spinel layer of the general composition (Cu,Mn,Cr)3-xO4. In addition, Cr-rich precipitates, formed in the dense layer close to coating/alloy interface. It is believed that these are Cr2O3 precipitates, formed when the solubility of Cr in the spinel phase is reached. Solubility experiments using powders showed that 1 mole of CuMn1.8O4 can effectively getter 1.83 moles of Cr2O3 at 800°C. Electrical conductivity of (Cu,Mn,Cr)3-xO4 was found to be at least two orders of magnitude higher than that of Cr2O3. The coatings acted as an effective Cr getter whose lifetime depends on the oxidation temperature, coating thickness, and the overall porosity in the coating. In-cell electrochemical testing showed that the CuMn1.8O4 coatings on Crofer 22 APU meshes performed significantly better than commercial Cu/Mn spinel coatings. The CuMn1.8O4 coatings gettered Cr effectively for 12 days at 800 ºC, leading to no performance loss of the cell due to Cr-poisoning. Significantly longer lifetime can be achieved at 750 ºC or lower, which is the target operational temperature regime of IT-SOFCs

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

A novel deep submicron bulk planar sizing strategy for low energy subthreshold standard cell libraries

Engineering andPhysical Science ResearchCouncil (EPSRC) and Arm Ltd for providing funding in the form of grants and studentshipsThis work investigates bulk planar deep submicron semiconductor physics in an attempt to improve standard cell libraries aimed at operation in the subthreshold regime and in Ultra Wide Dynamic Voltage Scaling schemes. The current state of research in the field is examined, with particular emphasis on how subthreshold physical effects degrade robustness, variability and performance. How prevalent these physical effects are in a commercial 65nm library is then investigated by extensive modeling of a BSIM4.5 compact model. Three distinct sizing strategies emerge, cells of each strategy are laid out and post-layout parasitically extracted models simulated to determine the advantages/disadvantages of each. Full custom ring oscillators are designed and manufactured. Measured results reveal a close correlation with the simulated results, with frequency improvements of up to 2.75X/2.43X obs erved for RVT/LVT devices respectively. The experiment provides the first silicon evidence of the improvement capability of the Inverse Narrow Width Effect over a wide supply voltage range, as well as a mechanism of additional temperature stability in the subthreshold regime. A novel sizing strategy is proposed and pursued to determine whether it is able to produce a superior complex circuit design using a commercial digital synthesis flow. Two 128 bit AES cores are synthesized from the novel sizing strategy and compared against a third AES core synthesized from a state-of-the-art subthreshold standard cell library used by ARM. Results show improvements in energy-per-cycle of up to 27.3% and frequency improvements of up to 10.25X. The novel subthreshold sizing strategy proves superior over a temperature range of 0 °C to 85 °C with a nominal (20 °C) improvement in energy-per-cycle of 24% and frequency improvement of 8.65X. A comparison to prior art is then performed. Valid cases are presented where the proposed sizing strategy would be a candidate to produce superior subthreshold circuits

Flat-plate solar array project. Volume 5: Process development

The goal of the Process Development Area, as part of the Flat-Plate Solar Array (FSA) Project, was to develop and demonstrate solar cell fabrication and module assembly process technologies required to meet the cost, lifetime, production capacity, and performance goals of the FSA Project. R&D efforts expended by Government, Industry, and Universities in developing processes capable of meeting the projects goals during volume production conditions are summarized. The cost goals allocated for processing were demonstrated by small volume quantities that were extrapolated by cost analysis to large volume production. To provide proper focus and coverage of the process development effort, four separate technology sections are discussed: surface preparation, junction formation, metallization, and module assembly