New CMOS Realization of Voltage Differencing Buffered Amplifier and Its Biquad Filter Applications

In this paper, new biquad filter configuration using a recently introduced active element, namely Voltage Differencing Buffered Amplifier (VDBA), is proposed. This block has high impedance input terminals and low impedance output terminal, providing advantages at voltage mode circuits. Besides, VDBA has a transconductance gain, thus the proposed circuits can be employed without using any external resistors. Two new voltage-mode biquad filter configurations are presented for VDBA application. Each proposed filter employs two active elements and two or three passive components. Filters, having three inputs and single output, can realize voltage-mode low-pass, band-pass, high-pass, band-stop, and all-pass filters. The biquad filters have low output impedances that is necessity for cascadability for voltage mode circuits, and no critical component matching conditions are required. For the second biquad, quality factor can be adjusted via resistor independently of the natural frequency. Simulation results are given to, confirming the theoretical analysis. The proposed biquad filters are simulated using TSMC CMOS 0.35 µm technology. LTSPICE simulations of the proposed circuits give results that agree well with the theoretical analysis

Biquadratic Filter Applications Using a Fully-Differential Active-Only Integrator

A new class of active filters, real active-only filters is described and possible implementation issues of these filters are discussed. To remedy these issues, a fully-differential active-only integrator block built around current controlled current conveyors is presented. The integration frequency of the proposed circuit is adjustable over a wide frequency range. As an application, a real active-only filter based on the classical two-integrator loop topology is presented and designed. The feasibility of this filter in a 0.35µm CMOS process is verified through SPECTRE simulation program in the CADENCE design tool

Design and standalone characterisation of a capacitively coupled HV-CMOS sensor chip for the CLIC vertex detector

The concept of capacitive coupling between sensors and readout chips is under study for the vertex detector at the proposed high-energy CLIC electron positron collider. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is an active High-Voltage CMOS sensor, designed to be capacitively coupled to the CLICpix2 readout chip. The chip is implemented in a commercial $180$ nm HV-CMOS process and contains a matrix of $128\times128$ square pixels with $25$ $\mu$m pitch. First prototypes have been produced with a standard resistivity of $\sim20$ $\Omega$cm for the substrate and tested in standalone mode. The results show a rise time of $\sim20$ ns, charge gain of $190$ mV/ke$^{-}$ and $\sim40$ e$^{-}$ RMS noise for a power consumption of $4.8$ $\mu$W/pixel. The main design aspects, as well as standalone measurement results, are presented.Comment: 13 pages, 13 figures, 2 tables. Work carried out in the framework of the CLICdp collaboratio

Tactile sensing chips with POSFET array and integrated interface electronics

This work presents the advanced version of novel POSFET (Piezoelectric Oxide Semiconductor Field Effect Transistor) devices based tactile sensing chip. The new version of the tactile sensing chip presented here comprises of a 4 x 4 array of POSFET touch sensing devices and integrated interface electronics (i.e. multiplexers, high compliance current sinks and voltage output buffers). The chip also includes four temperature diodes for the measurement of contact temperature. Various components on the chip have been characterized systematically and the overall operation of the tactile sensing system has been evaluated. With new design the POSFET devices have improved performance (i.e. linear response in the dynamic contact forces range of 0.01–3N and sensitivity (without amplification) of 102.4 mV/N), which is more than twice the performance of their previous implementations. The integrated interface electronics result in reduced interconnections which otherwise would be needed to connect the POSFET array with off-chip interface electronic circuitry. This research paves the way for CMOS (Complementary Metal Oxide Semiconductor) implementation of full on-chip tactile sensing systems based on POSFETs

A Low-Voltage Electronically Tunable MOSFET-C Voltage-Mode First-Order All-Pass Filter Design

This paper presents a simple electronically tunable voltage-mode first-order all-pass filter realization with MOSFET-C technique. In comparison to the classical MOSFET-C filter circuits that employ active elements including large number of transistors the proposed circuit is only composed of a single two n-channel MOSFET-based inverting voltage buffer, three passive components, and one NMOS-based voltage-controlled resistor, which is with advantage used to electronically control the pole frequency of the filter in range 103 kHz to 18.3 MHz. The proposed filter is also very suitable for low-voltage operation, since between its supply rails it uses only two MOSFETs. In the paper the effect of load is investigated. In addition, in order to suppress the effect of non-zero output resistance of the inverting voltage buffer, two compensation techniques are also introduced. The theoretical results are verified by SPICE simulations using PTM 90 nm level-7 CMOS process BSIM3v3 parameters, where +/- 0.45 V supply voltages are used. Moreover, the behavior of the proposed filter was also experimentally measured using readily available array transistors CD4007UB by Texas Instruments

2.5 V 35 dBm IIP3 75 MHz sixth-order active RC filter

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Study of Adjustable Gains for Control of Oscillation Frequency and Oscillation Condition in 3R-2C Oscillator

An idea of adjustable gain in order to obtain controllable features is very useful for design of tuneable oscillators. Several active elements with adjustable properties (current and voltage gain) are discussed in this paper. Three modified oscillator conceptions that are quite simple, directly electronically adjustable, providing independent control of oscillation condition and frequency were designed. Positive and negative aspects of presented method of control are discussed. Expected assumptions of adjustability are verified experimentally on one of the presented solution

A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects

Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands. This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture. Vertical-cavity surface-emitting laser (VCSEL) data rate is extended for a given average current and corresponding reliability level with a four-tap current summing FIR transmitter. A low-voltage integrating and double-sampling optical receiver front-end provides adequate sensitivity in a power efficient manner by avoiding linear high-gain elements common in conventional transimpedance-amplifier (TIA) receivers. Clock recovery is performed with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers. A prototype chip fabricated in 1 V 90 nm CMOS achieves 16 Gb/s operation while consuming 129 mW and occupying 0.105 mm^2