837 research outputs found
Design of Low Leakage Multi Threshold (Vth) CMOS Level Shifter
In this paper, a low leakage multi Vth level shifter is designed for robust voltage shifting from sub threshold to above threshold domain using MTCMOS technique and sleepy keeper. MTCMOS is an effective circuit level technique that improves the performance and design by utilizing both low and high threshold voltage transistors. Leakage power dissipation has become an overriding concern for VLSI circuit designers. In this a “sleepy keeper” approach is preferred which reduces the leakage current while saving exact logic state. The new low-power level shifter using sleepy keeper is compared with the previous work for different values of the lower supply voltage. When the circuits are individually analyzed for power consumption at 45nm CMOS technology, the new level shifter offer significant power savings up to 37% as compared to the previous work. Alternatively, when the circuits are individually analyzed for minimum propagation delay, speed is enhanced by up to 48% with our approach to the circuit. All the simulation results are based on 45nm CMOS technology and simulated in cadence tool.DOI:http://dx.doi.org/10.11591/ijece.v3i5.316
Advanced digital modulation: Communication techniques and monolithic GaAs technology
Communications theory and practice are merged with state-of-the-art technology in IC fabrication, especially monolithic GaAs technology, to examine the general feasibility of a number of advanced technology digital transmission systems. Satellite-channel models with (1) superior throughput, perhaps 2 Gbps; (2) attractive weight and cost; and (3) high RF power and spectrum efficiency are discussed. Transmission techniques possessing reasonably simple architectures capable of monolithic fabrication at high speeds were surveyed. This included a review of amplitude/phase shift keying (APSK) techniques and the continuous-phase-modulation (CPM) methods, of which MSK represents the simplest case
Recommended from our members
Micron-scale monolithically-integrated ultrasonic wireless sensing motes for physiological monitoring
There has been increasing interest in emerging implantable medical devices (IMDs) for continuous in vivo sensing of physiological signals, including temperature, PH, pressure, oxygen, and glucose, directly at the target locations. Many of these applications can benefit from wireless, miniaturized IMDs that eliminate the percutaneous power cords and facilitate the implantation procedures.
This thesis describes such a device for real-time in vivo monitoring of physiological temperature, such as the monitoring of core body temperature and temperature evaluation during thermal-related therapeutic procedures. Featuring a custom temperature sensor chip with a micron-scale piezoelectric transducer fabricated on top of the chip, the monolithic device, in the form of a mote, measures only 380 μm × 300 μm × 570 μm and weighs only 0.3 mg. The device utilizes ultrasound for wireless powering and communication through the on-chip transducer and achieves aggressive miniaturization through “chip-as-system” integration. The proposed motes were successfully validated in both in vitro experiments with animal tissues and in vivo settings with a mouse model. Compared to the state-of-the-art and equivalent commercial devices, the motes performed comparably or better in a fully-wireless manner while presenting a more compact form factor.
Such extreme miniaturization through monolithic integration enables multiple of these motes to be implanted/injected using minimally invasive surgeries with improved biocompatibility and reduced subject discomfort. This offers new approaches for localized in vivo monitoring of spatially-fine-grained temperature distributions and also provides a platform for sensing other types of physiological parameters
On the road towards robust and ultra low energy CMOS digital circuits using sub/near threshold power supply
Ph.DNUS-TU/E JOINT PH.D. PROGRAMM
System-on-chip Computing and Interconnection Architectures for Telecommunications and Signal Processing
This dissertation proposes novel architectures and design techniques targeting SoC building blocks for telecommunications and signal processing applications.
Hardware implementation of Low-Density Parity-Check decoders is approached at both the algorithmic and the architecture level. Low-Density Parity-Check codes are a promising coding scheme for future communication standards due to their outstanding error correction performance.
This work proposes a methodology for analyzing effects of finite precision arithmetic on error correction performance and hardware complexity. The methodology is throughout employed for co-designing the decoder. First, a low-complexity check node based on the P-output decoding principle is designed and characterized on a CMOS standard-cells library. Results demonstrate implementation loss below 0.2 dB down to BER of 10^{-8} and a saving in complexity up to 59% with respect to other works in recent literature. High-throughput and low-latency issues are addressed with modified single-phase decoding schedules. A new "memory-aware" schedule is proposed requiring down to 20% of memory with respect to the traditional two-phase flooding decoding. Additionally, throughput is doubled and logic complexity reduced of 12%. These advantages are traded-off with error correction performance, thus making the solution attractive only for long codes, as those adopted in the DVB-S2 standard. The "layered decoding" principle is extended to those codes not specifically conceived for this technique. Proposed architectures exhibit complexity savings in the order of 40% for both area and power consumption figures, while implementation loss is smaller than 0.05 dB.
Most modern communication standards employ Orthogonal Frequency Division Multiplexing as part of their physical layer. The core of OFDM is the Fast Fourier Transform and its inverse in charge of symbols (de)modulation. Requirements on throughput and energy efficiency call for FFT hardware implementation, while ubiquity of FFT suggests the design of parametric, re-configurable and re-usable IP hardware macrocells. In this context, this thesis describes an FFT/IFFT core compiler particularly suited for implementation of OFDM communication systems. The tool employs an accuracy-driven configuration engine which automatically profiles the internal arithmetic and generates a core with minimum operands bit-width and thus minimum circuit complexity. The engine performs a closed-loop optimization over three different internal arithmetic models (fixed-point, block floating-point and convergent block floating-point) using the numerical accuracy budget given by the user as a reference point. The flexibility and re-usability of the proposed macrocell are illustrated through several case studies which encompass all current state-of-the-art OFDM communications standards (WLAN, WMAN, xDSL, DVB-T/H, DAB and UWB). Implementations results are presented for two deep sub-micron standard-cells libraries (65 and 90 nm) and commercially available FPGA devices. Compared with other FFT core compilers, the proposed environment produces macrocells with lower circuit complexity and same system level performance (throughput, transform size and numerical accuracy).
The final part of this dissertation focuses on the Network-on-Chip design paradigm whose goal is building scalable communication infrastructures connecting hundreds of core. A low-complexity link architecture for mesochronous on-chip communication is discussed. The link enables skew constraint looseness in the clock tree synthesis, frequency speed-up, power consumption reduction and faster back-end turnarounds. The proposed architecture reaches a maximum clock frequency of 1 GHz on 65 nm low-leakage CMOS standard-cells library. In a complex test case with a full-blown NoC infrastructure, the link overhead is only 3% of chip area and 0.5% of leakage power consumption.
Finally, a new methodology, named metacoding, is proposed. Metacoding generates correct-by-construction technology independent RTL codebases for NoC building blocks. The RTL coding phase is abstracted and modeled with an Object Oriented framework, integrated within a commercial tool for IP packaging (Synopsys CoreTools suite). Compared with traditional coding styles based on pre-processor directives, metacoding produces 65% smaller codebases and reduces the configurations to verify up to three orders of magnitude
Towards Compact and High Speed Silicon Modulators
Los moduladores son elementos claves para la transmisión de la señal y el procesamiento de la información. Las técnicas de fabricación avanzadas "complementary metal-oxide semiconductor" (CMOS) permiten reducir drásticamente las dimensiones de estos dispositivos de interés para la implementación a gran escala en un chip de silicito a bajo coste. El trabajo realizado en esta tesis se centra en el diseño, la fabricación y la caracterización de estructuras de onda lenta con el objetivo de realizar moduladores compactos y eficientes integrados en un chip de silicio. El trabajo se divide en cuatro capítulos y un capítulo de conclusión y perspectivas. El capítulo uno introduce los fundamentos de física del estado sólido y de los mecanismos básicos de propagación guiada de la luz por reflexión total interna. El capítulo dos presenta los parámetros importantes de los moduladroes electro-ópticos así como un trabajo de recopilación de todos los mecanismos físicos que pueden ser empleados para modular la luz en silicio. Además, se presenta el estado del arte de los moduladores basados en silicio. El capítulo tres presenta el diseño , fabricación y caracterización de un modulador electro-óptico en silicio compacto y eficiente basado en el efecto de onda lenta en una estructura periódica unidimensional integrada, cuya geometría, similar a la de una red de Bragg, permite reducir la velocidad de grupo de un paquetes de ondas. Dicho efecto, se emplea para incrementar la interacción luz-materia y por lo tanto la eficiencia del modulador electro-óptico. El capítulo cuatro demuestra experimentalmente que dicha guía unidimensional periódica puede ser mejorada a fin de conseguir que el efecto de baja velocidad de grupo suceda en un rango mayor de longitudes de onda para posibles aplicaciones como la multiplexación por división de longitudinal de onda. En el capítulo cinco, se proporcionan conclusiones y perspectivas sobre el trabajo realizado.Brimont ., ACJ. (2011). Towards Compact and High Speed Silicon Modulators [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/14345Palanci
NEXT-100 Technical Design Report (TDR). Executive Summary
In this Technical Design Report (TDR) we describe the NEXT-100 detector that
will search for neutrinoless double beta decay (bbonu) in Xe-136 at the
Laboratorio Subterraneo de Canfranc (LSC), in Spain. The document formalizes
the design presented in our Conceptual Design Report (CDR): an
electroluminescence time projection chamber, with separate readout planes for
calorimetry and tracking, located, respectively, behind cathode and anode. The
detector is designed to hold a maximum of about 150 kg of xenon at 15 bar, or
100 kg at 10 bar. This option builds in the capability to increase the total
isotope mass by 50% while keeping the operating pressure at a manageable level.
The readout plane performing the energy measurement is composed of Hamamatsu
R11410-10 photomultipliers, specially designed for operation in low-background,
xenon-based detectors. Each individual PMT will be isolated from the gas by an
individual, pressure resistant enclosure and will be coupled to the sensitive
volume through a sapphire window. The tracking plane consists in an array of
Hamamatsu S10362-11-050P MPPCs used as tracking pixels. They will be arranged
in square boards holding 64 sensors (8 times8) with a 1-cm pitch. The inner
walls of the TPC, the sapphire windows and the boards holding the MPPCs will be
coated with tetraphenyl butadiene (TPB), a wavelength shifter, to improve the
light collection.Comment: 32 pages, 22 figures, 5 table
- …