Ultra low power high speed domino logic circuit by using FinFET technology

Scaling of the MOSFET face greater challenge by extreme power density due to leakage current in ultra deep sub-micron (UDSM) technology. To overcome from this situation double gate device like FinFET is used which has excellent control over the thin silicon fins with two electrically coupled gate, which mitigate shorter channel effect and exponentially reduces the leakage current. In this research paper utilize the property of FinFET in domino logic, for high speed operation and reduction of power consumption in wide fan-in OR gate. Proposed circuit is simulated in FinFET technology by BISM4 model using HSPICE at 32nm process technology at 250C with CL=1pF at 100MHz frequency. For 8 and 16 input OR gate we save average power 11.5%,11.39% in SFLD, 22.97%, 18.12% in HSD, 30.90%, 34.57% in CKD in SG mode and for LP mode 11.26%, 15.78% in SFLD, 19.74%, 17.94% in HSD, 45.23%, 34.69% in CKD respectivel

Design and Implementation of Novel High Performance Domino Logic

This dissertation presents design and implementation of novel high performance domino logic techniques with increased noise robustness and reduced leakages. The speed and overhead area became the primary parameters of choice for fabrication industry that led to invention of clocked logic styles named as Dynamic logic and Domino logic families. Most importantly, power consumption, noise immunity, speed of operation, area and cost are the predominant parameters for designing any kind of digital logic circuit technique with effective trade-off amongst these parameters depending on the situation and application of design. Because of its high speed and low overhead area domino logic became process of choice for designing of high speed application circuits. The concerning issues are large power consumption and high sensitivity towards noise. Hence, there is a need for designing new domino methodology to meet the requirements by overcoming above mentioned drawbacks which led to ample opportunities for diversified research in this field. Therefore, the outcome of research must be able to handle the primary design parameters efficiently. Besides this, the designed circuit must exhibit high degree of robustness towards noise.In this thesis, few domino logic circuit techniques are proposed to deal with noise and sub-threshold leakages. Effect of signal integrity issues on domino logic techniques is studied. Furthermore, having been subjected to process corner analysis and noise analysis, the overall performance of proposed domino techniques is found to be enhanced despite a few limitations that are mentioned in this work. Besides this, lector based domino and dynamic node stabilized techniques are also proposed and are investigated thoroughly. Simulations show that proposed circuits are showing superior performance. In addition to this, domino based Schmitt triggers with various hysteresis phenomena are designed and simulated. Pre-layout and post-layout simulation results are compared for proposed Schmitt trigger. Simulations reveal that proposed Schmitt trigger techniques are more noise tolerant than CMOS counterparts. Moreover, a test chip for domino based Schmitt trigger is done in UMC 180 nm technology for fabrication

Analysis of High-Performance Near-threshold Dual Mode Logic design

A novel dual mode logic (DML) model has a superior energy-performance compare to CMOS logic. The DML model has unique feature that allows switching between both modes of operation as per the real-time system requirements. The DML functions in two dissimilar modes (static and dynamic) of operation with its specific features, to selectively obtain either low-energy or high-performance. The sub-threshold region DML achieves minimum-energy. However, sub-threshold region consequence in performance is enormous. In this paper, the working of DML model in the moderate inversion region has been explored. The near-threshold region holds much of the energy saving of sub-threshold designs, along with improved performance. Furthermore, robustness to supply voltage and sensitivity to the process temperature variations are presented. Monte carol analysis shows that the projected near-threshold region has minimum energy along with the moderate performance

Energy Efficient Design for Deep Sub-micron CMOS VLSIs

Over the past decade, low power, energy efficient VLSI design has been the focal point of active research and development. The rapid technology scaling, the growing integration capacity, and the mounting active and leakage power dissipation are contributing to the growing complexity of modern VLSI design. Careful power planning on all design levels is required. This dissertation tackles the low-power, low-energy challenges in deep sub-micron technologies on the architecture and circuit levels. Voltage scaling is one of the most efficient ways for reducing power and energy. For ultra-low voltage operation, a new circuit technique which allows bulk CMOS circuits to work in the sub-0. 5V supply territory is presented. The threshold voltage of the slow PMOS transistor is controlled dynamically to get a lower threshold voltage during the active mode. Due to the reduced threshold voltage, switching speed becomes faster while active leakage current is increased. A technique to dynamically manage active leakage current is presented. Energy reduction resulting from using the proposed structure is demonstrated through simulations of different circuits with different levels of complexity. As technology scales, the mounting leakage current and degraded noise immunity impact performance especially that of high performance dynamic circuits. Dual threshold technology shows a good potential for leakage reduction while meeting performance goals. A model for optimally selecting threshold voltages and transistor sizes in wide fan-in dynamic circuits is presented. On the circuit level, a novel circuit level technique which handles the trade-off between noise immunity and energy dissipation for wide fan-in dynamic circuits is presented. Energy efficiency of the proposed wide fan-in dynamic circuit is further enhanced through efficient low voltage operation. Another direct consequence of technology scaling is the growing impact of interconnect parasitics and process variations on performance. Traditionally, worst case process, parasitics, and environmental conditions are considered. Designing for worst case guarantees a fail-safe operation but requires a large delay and voltage margins. This large margin can be recovered if the design can adapt to the actual silicon conditions. Dynamic voltage scaling is considered a key enabler in reducing such margin. An on-chip process identifier to recover the margin required due to process variations is described. The proposed architecture adjusts supply voltage using a hybrid between the one-time voltage setting and the continuous monitoring modes of operation. The interconnect impact on delay is minimized through a novel adaptive voltage scaling architecture. The proposed system recovers the large delay and voltage margins required by conventional systems by closely tracking the actual critical path at anytime. By tracking the actual critical path, the proposed system is robust and more energy efficient compared to both the conventional open-loop and closed-loop systems

Ultra Low Power Digital Circuit Design for Wireless Sensor Network Applications

Ny forskning innenfor feltet trådløse sensornettverk åpner for nye og innovative produkter og løsninger. Biomedisinske anvendelser er blant områdene med størst potensial og det investeres i dag betydelige beløp for å bruke denne teknologien for å gjøre medisinsk diagnostikk mer effektiv samtidig som man åpner for fjerndiagnostikk basert på trådløse sensornoder integrert i et ”helsenett”. Målet er å forbedre tjenestekvalitet og redusere kostnader samtidig som brukerne skal oppleve forbedret livskvalitet som følge av økt trygghet og mulighet for å tilbringe mest mulig tid i eget hjem og unngå unødvendige sykehusbesøk og innleggelser. For å gjøre dette til en realitet er man avhengige av sensorelektronikk som bruker minst mulig energi slik at man oppnår tilstrekkelig batterilevetid selv med veldig små batterier. I sin avhandling ” Ultra Low power Digital Circuit Design for Wireless Sensor Network Applications” har PhD-kandidat Farshad Moradi fokusert på nye løsninger innenfor konstruksjon av energigjerrig digital kretselektronikk. Avhandlingen presenterer nye løsninger både innenfor aritmetiske og kombinatoriske kretser, samtidig som den studerer nye statiske minneelementer (SRAM) og alternative minnearkitekturer. Den ser også på utfordringene som oppstår når silisiumteknologien nedskaleres i takt med mikroprosessorutviklingen og foreslår løsninger som bidrar til å gjøre kretsløsninger mer robuste og skalerbare i forhold til denne utviklingen. De viktigste konklusjonene av arbeidet er at man ved å introdusere nye konstruksjonsteknikker både er i stand til å redusere energiforbruket samtidig som robusthet og teknologiskalerbarhet øker. Forskningen har vært utført i samarbeid med Purdue University og vært finansiert av Norges Forskningsråd gjennom FRINATprosjektet ”Micropower Sensor Interface in Nanometer CMOS Technology”

Design and Analysis of Improved Domino Logic with Noise Tolerance and High Performance

The demands of upcoming computing, as well as the challenges of nanometer-era of VLSI design necessitate new digital logic techniques and styles that are at the same time high performance, energy efficient and robust to noise and variation. Dynamic CMOS logic gates are broadly used to design high performance circuits due to their high speed. Conversely, the vital demerit of dynamic logic style is its high noise sensitivity. The main reason for this is the sub-threshold leakage current flowing through the pull down network. With continuous technology scaling, this problem is getting more and more severe. In this thesis, a new noise tolerant dynamic CMOS circuit technique is proposed. In the proposed work, we have enhanced the behavior of the domino CMOS logic. This technique also gets benefit in terms of delay and power. This thesis describes the new low power, noise tolerant and high speed domino logic technique and presents a comparison result of this logic with previously reported schemes. Simulation results prove that, in 180 nm CMOS technology when we used this logic style to realize wide fan-in logic gates, it could achieve maximum level of noise robustness as compared to its basic counterpart. In addition, the logic also works efficiently with sequential circuits. The feasibility of this new technique is demonstrated by means of a real hardware, we have built a custom test-chip in the UMC 180 nm process technology with an ALU core, using the proposed domino logic style for each design block. In this thesis, we have also described the design and implementation of this chip. In addition to this, we have also presented initial power and delay performance comparisons between the circuit level simulated ALU and test-chip implemented in the proposed domino logic style. Finally we conclude that, the thesis contributes a very efficient logic style for wide fan-in gates, which is not only noise robust but also energy efficient and high speed

REVIEW OF HIGH-SPEED DIGITAL CMOS CIRCUITS

This paper presents a comprehensive review of the major state-of-the-art high-speed CMOS digital circuits. Focusing in particular on dynamic circuits such as conventional DOMINO, conditionalevaluation DOMINO and contention-free DOMINO. Also some high-performance non-dynamic (static) circuit techniques will be reviewed such as dual-threshold (DVT) circuits. The relative performance of these circuits in terms of speed, power, and noise margins is presented. Also the effects of technology scaling into the deep sub-micron regime on these techniques are evaluated and presented

FORCED STACK SLEEP TRANSISTOR (FORTRAN): A NEW LEAKAGE CURRENT REDUCTION APPROACH IN CMOS BASED CIRCUIT DESIGNING

Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design approach, experiments are conducted in the Tanner EDA tool of mentor graphics bundle on projected circuit designs for the full adder, a chain of 4-inverters, and 4-bit multiplier designs utilizing 180nm, 130nm, and 90nm TSMC technology node. The outcomes obtained show the result of a 95-98% vital reduction in leakage power as well as a 15-20% reduction in dynamic power with a minor increase in delay. The result outcomes are compared for accuracy with the notable design approaches that are accessible for both active and standby modes of operation

Study of Layout Techniques in Dynamic Logic Circuitry for Single Event Effect Mitigation

Dynamic logic circuits are highly suitable for high-speed applications, considering the fact that they have a smaller area and faster transition. However, their application in space or other radiation-rich environments has been significantly inhibited by their susceptibility to radiation effects. This work begins with the basic operations of dynamic logic circuits, elaborates upon the physics underlying their radiation vulnerability, and evaluates three techniques that harden dynamic logic from the layout: drain extension, pulse quenching, and a proposed method. The drain extension method adds an extra drain to the sensitive node in order to improve charge sharing, the pulse quenching scheme utilizes charge sharing by duplicating a component that offsets the transient pulse, and the proposed technique takes advantage of both. Domino buffers designed using these three techniques, along with a conventional design as reference, were modeled and simulated using a 3D TCAD tool. Simulation results confirm a significant reduction of soft error rate in the proposed technique and suggest a greater reduction with angled incidence. A 130 nm chip containing designed buffer and register chains was fabricated and tested with heavy ion irradiation. According to the experiment results, the proposed design achieved 30% soft error rate reduction, with 19%, 20%, and 10% overhead in speed, power, and area, respectively