58 research outputs found

    Two-Pass Rate Control for Improved Quality of Experience in UHDTV Delivery

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    Register-transfer level design of sum of absolute transformed difference for high efficiency video coding

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    High Efficiency Video Coding (HEVC) is the state-of-the-art video coding standard which offers 50% improvement in coding efficiency over its predecessor Advanced Video Coding (AVC). Compared to AVC, HEVC supports up to 33 angular modes, DC mode and planar mode. The significant rise in the number of intra prediction mode however has increased the computational complexity. Sum of Absolute Transformed Difference (SATD), a fast Rate Distortion Optimization (RDO) intra prediction algorithm in the HEVC standard, is one of the most complex and compute-intensive part of the encoding process. SATD alone can takes up to 40% of the total encoding time; hence off-loading it to dedicated hardware accelerators is necessary to address the increasing need for real-time video coding in accordance with the push for coding efficiency. This work proposes a Verilog-described N ร— N SATD hardware architecture which is based on Hadamard Transform. The architecture would support a variable block size from 4 ร— 4 to 32 ร— 32 with 1-D horizontal and 1-D vertical Hadamard Transform. At the same time, it is designed to achieve throughput optimization by pipelining and feedthrough control. The performance of the implemented SATD is then evaluated in terms of utilization, timing and power

    HEVC video compression hardware designs

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    High Efficiency Video Coding (HEVC), a recently developed international standard for video compression, offers significantly better video compression efficiency than previous international standards. However, this coding gain comes with an increase in computational complexity. Therefore, in this thesis, we first designed a high performance hardware architecture for deblocking filter algorithm used in HEVC standard. Two parallel datapaths are used in the hardware to increase its performance. The proposed hardware is implemented in Verilog HDL. The Verilog RTL code is mapped to a Xilinx XC6VLX240T FPGA, and it is verified to work correctly on a Xilinx ML605 FPGA board which includes a Xilinx XC6VLX240T FPGA. The FPGA implementation can work at 108 MHz, and it can code 30 full HD (1920x1080) video frames per second. We then proposed an energy reduction technique for Sum of Absolute Transformed Difference (SATD) based HEVC intra mode decision algorithm. We designed an efficient hardware architecture for SATD based HEVC intra mode decision algorithm including the proposed technique. The proposed hardware is implemented in Verilog HDL. The Verilog RTL code is mapped to a Xilinx XC6VLX365T FPGA, and it is verified with post place & route simulations. The FPGA implementation can work at 116 MHz, and it can code 21 HD (1280x720) video frames per second. The proposed technique reduced its energy consumption up to 64.6% on this FPGA without any PSNR loss

    A computation and energy reduction technique for HEVC intra mode decision

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    Fast Algorithms for HEVC Rate-Distortion Optimization

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    ํ•™์œ„๋…ผ๋ฌธ (๋ฐ•์‚ฌ)-- ์„œ์šธ๋Œ€ํ•™๊ต ๋Œ€ํ•™์› : ์ „๊ธฐยท์ปดํ“จํ„ฐ๊ณตํ•™๋ถ€, 2013. 8. ์ดํ˜์žฌ.๋””์ง€ํ„ธ ์˜์ƒ ๊ธฐ๊ธฐ์˜ ๋ฐœ์ „๊ณผ ๋”๋ถˆ์–ด, ๊ณ ํ™”์งˆ ์˜์ƒ์— ๋Œ€ํ•œ ์ˆ˜์š” ๋˜ํ•œ ํ•จ๊ป˜ ์ฆ๊ฐ€ํ•˜๊ณ  ์žˆ๋‹ค. ์ตœ๊ทผ์˜ ์Šค๋งˆํŠธํฐ๊ณผ ํƒœ๋ธ”๋ฆฟ PC์˜ ๊ธ‰์†์ ์ธ ์„ฑ์žฅ์€ ์ด๋Ÿฌํ•œ ์ถ”์„ธ๋ฅผ ๊ฐ€์†ํ™” ์‹œํ‚ค๊ณ  ์žˆ๋‹ค. ์ด๋Ÿฌํ•œ ๋ณ€ํ™”์— ๋งž์ถ”์–ด, ๊ณ ํ™”์งˆ ์˜์ƒ ์••์ถ•์„ ์œ„ํ•œ ์ƒˆ๋กœ์šด ์˜์ƒ ์••์ถ• ๊ธฐ์ˆ ์˜ ํ‘œ์ค€ํ™”๊ฐ€ ISO/IEC MPEG๊ณผ ITU-T/VCEG์˜ ๊ณต๋™์˜ ํŒ€์œผ๋กœ ์ง„ํ–‰๋˜์–ด ์™”๋‹ค. HEVC๋Š” H.264/AVC์˜ ๋’ค๋ฅผ ์ž‡๋Š” ์ฐจ์„ธ๋Œ€ ์˜์ƒ ์••์ถ• ํ‘œ์ค€ ๊ธฐ์ˆ ๋กœ์„œ, 2013๋…„ 1์›” FDIS (Final Draft International Standard)๊ฐ€ ์ž‘์„ฑ๋˜๋ฉด์„œ, ํ‘œ์ค€ํ™” ๊ณผ์ •์ด ์™„๋ฃŒ๋˜์—ˆ๋‹ค. HEVC๋Š” H.264/AVC ๋Œ€๋น„ ๊ฐ™์€ ํ™”์งˆ์˜ ์˜์ƒ์„ ์ ˆ๋ฐ˜์˜ ๋น„ํŠธ๋Ÿ‰์œผ๋กœ ์••์ถ•ํ•˜๋Š” ๊ฒƒ์„ ๋ชฉํ‘œ๋กœ ํ•˜์˜€์œผ๋ฉฐ, ์ด๋Ÿฐ ๋ชฉํ‘œ๋ฅผ ๋‹ฌ์„ฑํ•˜๊ธฐ ์œ„ํ•ด, ์ƒˆ๋กœ์šด ๊ธฐ์ˆ ๋“ค์ด ์ œ์•ˆ๋˜์—ˆ๋‹ค. ํŠนํžˆ, ๋ณต์žกํ•œ block ๊ตฌ์กฐ์™€ ํฌ๊ฒŒ ๋Š˜์–ด๋‚œ mode์˜ ์ˆ˜๋Š” ์˜์ƒ ์••์ถ•์˜ ํšจ์œจ์„ ํ–ฅ์ƒ์‹œํ‚ค๋Š” ๋ฐ์— ํฌ๊ฒŒ ๊ธฐ์—ฌ๋ฅผ ํ•˜์˜€๊ณ , ์ด๋Š” ์ตœ์ ์˜ mode๋ฅผ ๊ฒฐ์ •ํ•˜๋Š” RDO (Rate-Distortion Optimization)๊ฐ€ ๋”์šฑ ์ค‘์š”ํ•œ ์—ญํ• ์„ ํ•˜๋„๋ก ๋งŒ๋“ค์—ˆ๋‹ค. ๊ทธ๋Ÿฌ๋‚˜, ๋ณต์žกํ•ด์ง„ block ๊ตฌ์กฐ๋Š” RDO์˜ ์—ฐ์‚ฐ๋Ÿ‰ ๋˜ํ•œ ํฌ๊ฒŒ ์ฆ๊ฐ€์‹œ์ผฐ๋‹ค. ์ด๋Ÿฌํ•œ ์ด์œ ๋กœ, H.264/AVC์™€ ๋‹ฌ๋ฆฌ HEVC์—์„œ๋Š” RDO์˜ ์—ฐ์‚ฐ๋Ÿ‰์„ ์ค„์ด๋ฉด์„œ ์••์ถ• ํšจ์œจ์„ ์œ ์ง€ํ•˜๋Š” ๊ฒƒ์ด ์ค‘์š”ํ•œ ์ด์Šˆ๊ฐ€ ๋˜์—ˆ๋‹ค. ๋ณธ ๋…ผ๋ฌธ์—์„œ๋Š”, H.264/AVC์™€ HEVC์—์„œ์˜ RDO์— ์˜ํ•œ RD ์ €ํ•˜์˜ ์ฐจ์ด๋ฅผ ์‹คํ—˜ ๊ฒฐ๊ณผ๋ฅผ ํ†ตํ•ด ์ œ์‹œํ•˜์—ฌ ๋ฌธ์ œ๋ฅผ ์ •์˜ํ•˜๊ณ , RDO์˜ ์—ฐ์‚ฐ๋Ÿ‰์„ ์ค„์ด๋Š” ์•Œ๊ณ ๋ฆฌ์ฆ˜๋“ค์„ ์„ธ ๊ฐ€์ง€ ์—ฐ๊ตฌ ๋ฐฉํ–ฅ์„ ํ†ตํ•ด ์ œ์•ˆํ•˜์˜€๋‹ค. ์ฒซ ๋ฒˆ์งธ ๋ฐฉํ–ฅ์˜ ์—ฐ๊ตฌ์—์„œ๋Š” RDO์˜ ๊ณผ์ •์„ ๊ตฌ์„ฑํ•˜๋Š” Transform, Quantization, Inverse Quantization, Inverse Transform ๊ทธ๋ฆฌ๊ณ  Entropy Coder ๋“ฑ์˜ ์ผ๋ จ์˜ ๊ณผ์ •์˜ ์—ฐ์‚ฐ์„ ๋‹จ์ˆœํ™”ํ•˜๋Š” ์•Œ๊ณ ๋ฆฌ์ฆ˜๋“ค์ด ์ œ์•ˆ๋˜์—ˆ๋‹ค. ์ด๋Ÿฌํ•œ ์•Œ๊ณ ๋ฆฌ์ฆ˜์€ ๊ธฐ๋ณธ์ ์œผ๋กœ H.264/AVC์—์„œ ์ด๋ฃจ์–ด์ง„ ์—ฐ๊ตฌ๋ฅผ ๊ธฐ๋ฐ˜์œผ๋กœ ํ•˜์˜€๊ณ , ๊ธฐ์กด ์•Œ๊ณ ๋ฆฌ์ฆ˜์˜ ํ•œ๊ณ„ ๋˜ํ•œ ๋ถ„์„๋˜์–ด ์„ฑ๋Šฅ์„ ํ–ฅ์ƒ์‹œ์ผฐ๋‹ค. ๋” ๋‚˜์•„๊ฐ€์„œ๋Š”, ์ข€ ๋” ๊ณต๊ฒฉ์ ์œผ๋กœ RDO์˜ ์—ฐ์‚ฐ๋Ÿ‰์„ ์ค„์ผ ์ˆ˜ ์žˆ๋Š” ์ƒˆ๋กœ์šด ๋ฐฉ๋ฒ•์„ ์ œ์•ˆํ•˜์˜€๋‹ค. ๋‘ ๋ฒˆ์งธ ๋ฐฉํ–ฅ์˜ ์—ฐ๊ตฌ์—์„œ๋Š” Zero Block detection์ด๋ผ๋Š” ๊ธฐ์ˆ ์„ ๊ธฐ๋ฐ˜์œผ๋กœ, HEVC์— ์ ํ•ฉํ•˜๊ฒŒ RDO์˜ ์—ฐ์‚ฐ์„ ์ค„์ด๋Š” ๋ฐฉ๋ฒ•์„ ์ œ์•ˆํ•˜์˜€๋‹ค. H.264/AVC์—์„œ ์ œ์•ˆ๋˜์—ˆ๋˜ ์•Œ๊ณ ๋ฆฌ์ฆ˜๋“ค์€ HEVC์—์„œ์˜ Zero Block์„ ํŠน์ง•์„ ์ œ๋Œ€๋กœ ๋ฐ˜์˜ํ•˜์ง€ ๋ชปํ•˜๊ธฐ ๋•Œ๋ฌธ์—, ๋‹จ์ˆœ ์ˆ˜์ •์„ ํ†ตํ•ด HEVC์— ์ ์šฉํ•  ๊ฒฝ์šฐ ๊ธฐ๋Œ€ํ•œ ๋งŒํผ์˜ ์„ฑ๋Šฅ์„ ์–ป์„ ์ˆ˜ ์—†๋‹ค. ์ด๋Ÿฌํ•œ ํ•œ๊ณ„์ ์„ ํ•ด๊ฒฐํ•˜์—ฌ HEVC์— ์ ํ•ฉํ•œ ํšจ์œจ์ ์ธ Zero Block detection ์•Œ๊ณ ๋ฆฌ์ฆ˜์ด ์ œ์‹œ๋˜์—ˆ๋‹ค. ์„ธ ๋ฒˆ์งธ ๋ฐฉํ–ฅ์˜ ์—ฐ๊ตฌ์—์„œ๋Š”, SATD ๊ธฐ๋ฐ˜์˜ RDO๋ฅผ ํ™œ์šฉํ•˜์—ฌ, SSE ๊ธฐ๋ฐ˜์˜ RDO์˜ ์—ฐ์‚ฐ๋Ÿ‰์„ ์ค„์ด๋Š” ๋ฐฉ๋ฒ•์„ ์ œ์•ˆํ•˜์˜€๋‹ค. SATD ๊ธฐ๋ฐ˜์˜ RDO์™€ SSE ๊ธฐ๋ฐ˜์˜ RDO์˜ ์ฐจ์ด์  ๋ถ„์„๊ณผ ์‹คํ—˜ ๊ฒฐ๊ณผ ๋ฐ”ํƒ•์œผ๋กœ ํšจ์œจ์ ์œผ๋กœ SATD ๊ธฐ๋ฐ˜์˜ RDO์„ ํ™œ์šฉํ•˜๋Š” ๋ฐฉ๋ฒ•์ด ์ œ์‹œ๋˜์—ˆ๋‹ค. ์ด๋ ‡๊ฒŒ ์ œ์•ˆ๋œ ์•Œ๊ณ ๋ฆฌ์ฆ˜๋“ค์€ HEVC์˜ reference software์ธ HM์— ๊ตฌํ˜„๋˜์–ด, RDO์˜ ์—ฐ์‚ฐ๋Ÿ‰์„ ํฌ๊ฒŒ ์ค„์ด๋ฉด์„œ๋„, RD ์ €ํ•˜๊ฐ€ ํฌ๊ฒŒ ์ฆ๊ฐ€ํ•˜์ง€ ์•Š๋Š” ์‹คํ—˜ ๊ฒฐ๊ณผ๋ฅผ ๋ณด์ด๊ณ  ์žˆ๋‹ค.์ดˆ๋ก iii ๋ชฉ์ฐจ v ํ‘œ ๋ชฉ์ฐจ viii ๊ทธ๋ฆผ ๋ชฉ์ฐจ x ์ œ 1 ์žฅ ์„œ๋ก  1 1.1 ์—ฐ๊ตฌ ๋ฐฐ๊ฒฝ 1 1.2 ์—ฐ๊ตฌ ๋‚ด์šฉ 3 1.3 ๋…ผ๋ฌธ ๊ตฌ์„ฑ 6 ์ œ 2 ์žฅ ๋ฐฐ๊ฒฝ์ง€์‹๊ณผ ์ด์ „ ์—ฐ๊ตฌ 7 2.1 ๋ฐฐ๊ฒฝ์ง€์‹ 7 2.2 ์ด์ „ ์—ฐ๊ตฌ 15 ์ œ 3 ์žฅ Simplified RDO 19 3.1 Simplified SSE 19 3.2 Simplified CABAC 24 3.2.1 CABAC์˜ ๊ตฌ์กฐ 24 3.2.2 Various Complexity CABAC 25 3.2.2.1 High-Complexity CABAC 25 3.2.2.2 Medium-Complexity CABAC 26 3.2.2.3 Low-Complexity CABAC 22 3.2.2.4 Evaluation of Various Complexity CABAC 29 3.2.3 Low-Complexity CABAC for HEVC 30 3.3 Advanced Simplified SSE & CABAC 37 3.3.1 Threshold Algorithm 37 3.3.2 Simplified SSE & CABAC without Transform 41 3.4 Evaluation 48 ์ œ 4 ์žฅ Zero Block Detection 51 4.1 Extension of H.264/AVC Zero Block Detection for HEVC 51 4.1.1 Characteristics of the zero blocks in HEVC 51 4.1.2 ZB detection by an extension of the H.264/AVC algorithm 54 4.2 Zreo Block Detection for HEVC 59 4.2.1 GZB Detection for 16x16 and 32x32 transforms 59 4.2.2 Relaxed conditions for PZB detection 62 4.2.3 Further complexity reduction with SAD(or SATD) test 65 4.2.4 Proposed ZB detection for HEVC 72 4.3 Evaluation 74 ์ œ 5 ์žฅ SATD based RDO EVALUATION 84 5.1 Difference between SSE based RDO and SATD based RDO 84 5.2 SATD based RDO Evaluation for HEVC 88 5.3 Evaluation 93 ์ œ 6 ์žฅ ๊ฒฐ๋ก  95Docto
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