Transmit Diversity Code Filter Sets (TDCFSs), an MISO Antenna Frequency Predistortion Scheme for ATSC 3.0

"(c) 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.")Transmit diversity code filter sets (TDCFSs) are a method of predistorting the common waveforms from multiple transmitters in the same frequency channel, as in a single frequency network, in order to minimize the possibility of cross-interference among the transmitted signals over the entire reception area. This processing is achieved using all-pass linear filters, allowing the resulting combination of predistortion and multipath to be properly compensated as part of the equalization process in the receiver. The filter design utilizes an iterative computational approach, which minimizes cross-correlation peak side lobe under the constraints of number of transmitters and delay spread, allowing customization for specific network configurations. This paper provides an overview of the TDCFS multiple-input single output antenna scheme adopted in ATSC 3.0, together with experimental analysis of capacity and specific worst-case conditions that illustrate the benefits of using the TDCFS approach.Lopresto, S.; Citta, R.; Vargas, D.; Gómez Barquero, D. (2016). Transmit Diversity Code Filter Sets (TDCFSs), an MISO Antenna Frequency Predistortion Scheme for ATSC 3.0. IEEE Transactions on Broadcasting. 62(1):271-280. doi:10.1109/TBC.2015.2505400S27128062

Hardware architecture implemented on FPGA for protecting cryptographic keys against side-channel attacks

This paper presents a new hardware architecture designed for protecting the key of cryptographic algorithms against attacks by side-channel analysis (SCA). Unlike previous approaches already published, the fortress of the proposed architecture is based on revealing a false key. Such a false key is obtained when the leakage information, related to either the power consumption or the electromagnetic radiation (EM) emitted by the hardware device, is analysed by means of a classical statistical method. In fact, the trace of power consumption (or the EM) does not reveal any significant sign of protection in its behaviour or shape. Experimental results were obtained by using a Virtex 5 FPGA, on which a 128-bit version of the standard AES encryption algorithm was implemented. The architecture could easily be extrapolated to an ASIC device based on standard cell libraries. The system is capable of concealing the real key when various attacks are performed on the AES algorithm, using two statistical methods which are based on correlation, the Welch’s t-test and the difference of means.Peer ReviewedPostprint (author's final draft