Study and application of direct RF power injection methodology and mitigation of electromagnetic interference in ADCs

There are many publications available in literature regarding the DPI (Direct Power Injection) technique for electronic systems, but few works specifically addressed for mixed-signal converters, which are components existent in almost all electronic devices. IEC 62132-4(International Electrotechnical Commission, 2006) and 62132-1(International Electrotechnical Commission, 2006) standards describe a method for measuring immunity of integrated circuits (IC) in the presence of conducted RF disturbances. This method ensures a high degree of repeatability and correlation of immunity measurements. Knowledge of the electromagnetic immunity of an IC allows the designer to decide if the system will need external protection, and how much effort should be directed to this solution. In this context, the purpose of this work is the study and application of the DPI methodology for injection of EMI in a mixed-signal programmable device, evaluating mitigation possibilities, with special focus on the analog-to-digital converters (ADCs). The main objective is to evaluate the impact of electromagnetic interference (EMI) on different converters (two Successive Approximation Register ADCs, operating with distinct sampling rate and a Sigma-Delta ADC) of the Cypress Semiconductor Programmable SoC (System-on-Chip), PSoC 5LP. Additionally a previously proposed fault tolerance methodology, based on triplication with hardware and time diversity is tested. Results show distinct behaviors of each converter to conducted EMI. Finally, the tested tolerance technique showed to be suitable to reduce error rate of such data acquisition system operating under EMI disturbance.Existem muitas publicações disponíveis na literatura sobre a técnica de DPI (Direct Power Injection ou injeção direta de energia) para sistemas eletrônicos, mas poucos trabalhos direcionados para conversores de sinais mistos, que são componentes existentes em quase todos os dispositivos eletrônicos. As normas IEC 62132-4 (IEC, 2006) e 62132-1 (IEC, 2006) descrevem um método para medir a imunidade de circuitos integrados (CI) na presença de distúrbios de RF conduzidos. Este método garante um alto grau de repetibilidade e correlação das medições da imunidade. O conhecimento da imunidade eletromagnética de um CI permite que o projetista decida se o sistema precisará de proteção externa e quanto esforço deve ser direcionado para esta solução. Nesse contexto, o objetivo deste trabalho é o estudo e aplicação da metodologia DPI para injeção de interferência eletromagnética em um dispositivo programável de sinal misto, avaliando as possibilidades de mitigação, com foco especial em conversores analógico-digitais (ADCs). O principal objetivo é avaliar o impacto da interferência eletromagnética em diferentes conversores (dois ADCs baseados em aproximação sucessiva, operando com taxa de amostragem distintas e um ADC do tipo Sigma-Delta) do SoC(System-on-Chip) programável da Cypress Semiconductor, PSoC 5LP. Além disso, é testada uma metodologia de tolerância a falhas proposta anteriormente, baseada em triplicação com diversidade de hardware e temporal. Os resultados mostram comportamentos distintos de cada conversor para a interferência eletromagnética conduzida. Finalmente, a técnica de tolerância testada mostrou-se adequada para reduzir a taxa de erros desse sistema de aquisição de dados operando sob perturbação eletromagnética

The synthesis of a mobile computerized health testing system

M.S.Joseph J. Talavag

A Fast Digital Integrator for magnetic measurements

In this work, the Fast Digital Integrator (FDI), conceived for characterizing dynamic features of superconducting magnets and measuring fast transients of magnetic fields at the European Organization for Nuclear Research (CERN) and other high-energy physics research centres, is presented. FDI development was carried out inside a framework of cooperation between the group of Magnet Tests and Measurements of CERN and the Department of Engineering of the University of Sannio. Drawbacks related to measurement time decrease of main high-performance analog-to-digital architectures, such as Sigma-Delta and integrators, are overcome by founding the design on (i) a new generation of successive-approximation converters, for high resolution (18-bit) at high rate (500 kS/s), (ii) a digital signal processor, for on-line down-sampling by integrating the input signal, (iii) a custom time base, based on a Universal Time Counter, for reducing time-domain uncertainty, and (iv) a PXI board, for high bus transfer rate, as well as noise and heat immunity. A metrological analysis, aimed at verifying the effect of main uncertainty sources, systematic errors, and design parameters on the instrument performance is presented. In particular, results of an analytical study, a preliminary numerical analysis, and a comprehensive multi-factor analysis carried out to confirm the instrument design, are reported. Then, the selection of physical components and the FDI implementation on a PXI board according to the above described conceptual architecture are highlighted. The on-line integration algorithm, developed on the DSP in order to achieve a real-time Nyquist bandwidth of 125 kHz on the flux, is described. C++ classes for remote control of FDI, developed as a part of a new software framework, the Flexible Framework for Magnetic Measurements, conceived for managing a wide spectrum of magnetic measurements techniques, are described. Experimental results of metrological and throughput characterization of FDI are reported. In particular, in metrological characterization, FDI working as a digitizer and as an integrator, was assessed by means of static, dynamic, and time base tests. Typical values of static integral nonlinearity of ±7 ppm, ±3 ppm of 24-h stability, and 108 dB of signal-to-noise-anddistortion ratio at 10 Hz on Nyquist bandwidth of 125 kHz, were surveyed during the integrator working. The actual throughput rate was measured by a specific procedure of PXI bus analysis, by highlighting typical values of 1 MB/s. Finally, the experimental campaign, carried out at CERN facilities of superconducting magnet testing for on-field qualification of FDI, is illustrated. In particular, the FDI was included in a measurement station using also the new generation of fast transducers. The performance of such a station was compared with the one of the previous standard station used in series tests for qualifying LHC magnets. All the results highlight the FDI full capability of acting as the new de-facto standard for high-performance magnetic measurements at CERN and in other high-energy physics research centres

Spaceborne memory organization, an associative data acquisition system, phase II Final report, Apr. - Dec. 1966

Spaceborne memory organization, associative data acquisition system design, and data compression technique

The 1992 4th NASA SERC Symposium on VLSI Design

Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design

A study of low cost approaches to scientific experiment implementation for shuttle launched and serviced automated spacecraft

Cost reductions that can be obtained in experiment instrumentation by the use of standardized electronics and by the relaxation of instrument reliability requirements are studied. The feasibility of using standardized equipment for experiment instrumentation is assessed and a system design approach that most effectively incorporates standardized equipment is developed. The level and form of modularization that is appropriate for the standardized equipment is determined. Mission assurance aspects of instrument development are examined to determine the cost reductions that might be derived from the relaxation of reliability requirements and to formulate a systematic approach to the optimization of mission assurance cost reductions. The results of the analyses are applied to a representative model HEAO payload in order to provide a concrete example of the cost reductions that can be achieved by a standardized approach to the instrument electronics

Data systems elements technology assessment and system specifications, issue no. 2

The ability to satisfy the objectives of future NASA Office of Applications programs is dependent on technology advances in a number of areas of data systems. The hardware and software technology of end-to-end systems (data processing elements through ground processing, dissemination, and presentation) are examined in terms of state of the art, trends, and projected developments in the 1980 to 1985 timeframe. Capability is considered in terms of elements that are either commercially available or that can be implemented from commercially available components with minimal development

A modular neural interface for massively parallel recording and control : subsystem design considerations for research and clinical applications

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.Cataloged from PDF version of thesis.Includes bibliographical references (p. 78-79).The closed-loop Brain-Machine Interface (BMI) has long been a dream for clinicians and neuroscience researchers alike - that is, the ability to extract meaningful information from the brain, perform computation on this information, and selectively perturb neural dynamics in the brain for therapeutic benefit to the patient. Such systems have immediate application to treatment of paralysis, epilepsy and the amputated, and the potential for treatment of higher order cognitive dysfunction. Despite the promise of the BMI concept, the technology for bidirectional communication with the brain at sufficiently large scale to be truly therapeutically useful is lacking. Current state-of-the-art neuromodulation systems deliver open loop, 16-channel patterned electrical stimulation incapable of precisely targeting small numbers of neurons. Large-scale neural recording systems are limited to 16-128 electrodes, at the cost of several thousand dollars per channel. The ability to record from the awake behaving animal - let alone precisely modulate neural network dynamics in closed-loop fashion- presents a substantial challenge today.In this thesis, I present decoupled design solutions for three critical subcomponents of the closed-loop BMI - (i) a highly miniature, wirelessly powered and wirelessly controlled implantable optogenetic neuromodulation system capable of selective neural network control with single neural subtype- and millisecond-timescale precision, (ii) a prototype, highly parallel and scalable bio-potential recording system for simultaneous monitoring of many thousands of electrodes, and (iii) a space- and energy-efficient battery charger for biomedical applications. In aggregate, these systems overcome many of the fundamental architectural problems seen in the research and clinical environment today, potentially enabling a new class of neuromodulation system capable of treatment of higher-order cognitive dysfunction. In the research setting, these systems may be scaled to enable whole-brain recording, potentially yielding insights into large-scale neural network dynamics underlying disease and cognition.by Christian T. Wentz.M.Eng

A superconducting bandpass delta-sigma modulator for direct analog-to-digital conversion of microwave radio

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.Includes bibliographical references (p. 291-305).This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Direct analog-to-digital conversion of multi-GHz radio frequency (RF) signals is the ultimate goal in software radio receiver design but remains a daunting challenge for any technology. This thesis examines the potential of superconducting technology for realizing RF analog-to-digital converters (ADCs) with improved performance. A bandpass delta-sigma (AE) modulator is an attractive architecture for digitizing narrowband signals with high linearity and a large signal-to-noise ratio (SNR). The design of a superconducting bandpass AE modulator presented here exploits several advantages of superconducting electronics: the high quality factor of resonators, the high sampling rates of comparators realized with Josephson junctions, natural quantization of voltage pulses, and high circuit sensitivity. Demonstration of a superconducting circuit operating at clock rates in the tens of GHz is often hindered by the difficulty of high speed interfacing with room-temperature test equipment. In this work, a test chip with integrated acquisition memory is used to simplify high speed testing in a cryogenic environment. The small size (256 bits) of the on-chip memory severely limits the frequency resolution of spectra based on standard fast Fourier transforms. Higher resolution spectra are obtained by "segmented correlation", a new method for testing ADCs. Two different techniques have been found for clocking the superconducting modulator at frequencies in the tens of GHz. In the first approach, an optical clocking technique was developed, in which picosecond laser pulses are delivered via optical fiber to an on-chip metal-semiconductor-metal (MSM) photodiode, whose output current pulses trigger the Josephson circuitry. In the second approach, the superconducting modulator is clocked by an on-chip Josephson oscillator.(cont.) These testing methods have been applied in the successful demonstration of a super-conducting bandpass AE modulator fabricated in a niobium integrated circuit process with 1 kA/cm2 critical current density for the Josephson junctions. At a 42.6 GHz sampling rate, the center frequency of the experimental modulator is 2.23 GHz, the measured SNR is 49 dB over a 20.8 MHz bandwidth, and a full-scale (FS) input is -17.4 dBm. At a 40.2 GHz sampling rate, the measured in-band noise is -57 dBFS over a 19.6 MHz bandwidth.by John Francis Bulzacchelli.Ph.D