New techniques for the design and implementation of efficient full-search algorithms for block-matching motion estimation

The block-matching motion estimation (BME) is one of the most commonly used techniques for digital video compression in low to moderate bit rate environments. The full search for block-matching motion estimation, as compared to a partial search, provides a higher motion estimation accuracy, yet its computational cost is generally high. Hence, developing new techniques for an efficient implementation of full-search algorithms is of practical significance for the BME. In this thesis, a new full search algorithm is proposed, wherein the mean squared error (MSE) is used as the matching criterion to provide a higher motion estimation accuracy for the BME than that by any algorithm based on the most commonly-used mean absolute difference. It is shown that the computation of the MSE in the Haar wavelet domain results in a computational complexity that is much lower than or of the same order as that of the best-performing full search algorithms available in the literature. A new approach has been developed for the multi-reference-frame block-matching motion estimation, wherein a full search is performed in the spatial domain of the multi-reference-frame memory, and an early termination is imposed in the temporal domain using a novel strategy. It is shown that the computational complexity of the proposed full search method is significantly lower than that of any existing full search technique, and yet has a motion estimation accuracy which is about the same as that of the latter. A new pseudo-spiral-scan data input scheme has been proposed, which can be used in any existing hardware architecture for the implementation of the successive-elimination-based block-matching motion estimation. This scheme results in significant power savings compared to the conventional raster-scan data input scheme. Several designs to implement the successive elimination algorithm have been given, some of which are shown to provide additional power savings

Efficient hardware implementations of low bit depth motion estimation algorithms

In this paper, we present efficient hardware implementation of multiplication free one-bit transform (MF1BT) based and constraint one-bit transform (C-1BT) based motion estimation (ME) algorithms, in order to provide low bit-depth representation based full search block ME hardware for real-time video encoding. We used a source pixel based linear array (SPBLA) hardware architecture for low bit depth ME for the first time in the literature. The proposed SPBLA based implementation results in a genuine data flow scheme which significantly reduces the number of data reads from the current block memory, which in turn reduces the power consumption by at least 50% compared to conventional 1BT based ME hardware architecture presented in the literature. Because of the binary nature of low bit-depth ME algorithms, their hardware architectures are more efficient than existing 8 bits/pixel representation based ME architectures

A high performance hardware architecture for one bit transform based motion estimation

Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (IBT) based ME algorithms have low computational complexity. Therefore, in this paper, we propose a high performance systolic hardware architecture for IBT based ME. The proposed hardware performs full search ME for 4 Macroblocks in parallel and it is the fastest IBT based ME hardware reported in the literature. In addition, it uses less on-chip memory than the previous IBT based ME hardware by using a novel data reuse scheme and memory organization. The proposed hardware is implemented in Verilog HDL. It consumes %34 of the slices in a Xilinx XC2VP30-7 FPGA. It works at 115 MHz in the same FPGA and is capable of processing 50 1920x1080 full High Definition frames per second. Therefore, it can be used in consumer electronics products that require real-time video processing or compression

Dynamically variable step search motion estimation algorithm and a dynamically reconfigurable hardware for its implementation

Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. For the recently available High Definition (HD) video formats, the computational complexity of De full search (FS) ME algorithm is prohibitively high, whereas the PSNR obtained by fast search ME algorithms is low. Therefore, ill this paper, we present Dynamically Variable Step Search (DVSS) ME algorithm for Processing high definition video formats and a dynamically reconfigurable hardware efficiently implementing DVSS algorithm. The architecture for efficiently implementing DVSS algorithm. The simulation results showed that DVSS algorithm performs very close to FS algorithm by searching much fewer search locations than FS algorithm and it outperforms successful past search ME algorithms by searching more search locations than these algorithms. The proposed hardware is implemented in VHDL and is capable, of processing high definition video formats in real time. Therefore, it can be used in consumer electronics products for video compression, frame rate up-conversion and de-interlacing(1)

Evolutionary strategy based improved motion estimation technique for H.264 video coding

In this paper we propose an improved motion estimation algorithm based on evolutionary strategy (ES) for H.264 video codec applied to video. The proposed technique works in a parallel local search for macroblocks. For this purpose (mu+lambda) ES is used with an initial population of heuristically and randomly generated motion vectors. Experimental results show that the proposed scheme can reduce the computational complexity up to 50% of the motion estimation algorithm used in the H.264 reference codec at the same picture quality. Therefore, the proposed algorithm provides a significant improvement in motion estimation in the H.264 video codec

Hardware acceleration architectures for MPEG-Based mobile video platforms: a brief overview

This paper presents a brief overview of past and current hardware acceleration (HwA) approaches that have been proposed for the most computationally intensive compression tools of the MPEG-4 standard. These approaches are classified based on their historical evolution and architectural approach. An analysis of both evolutionary and functional classifications is carried out in order to speculate on the possible trends of the HwA architectures to be employed in mobile video platforms