Skew detection and compensation for Internet audio applications

Long lived audio streams, such as music broadcasts, and small differences in clock rates lead to buffer underflow or overflow events in receiving applications that manifest themselves as audible interruptions. We present a low complexity algorithm for detecting clock skew in network audio applications that function with local clocks and in the absence of a synchronization mechanism. A companion algorithm to perform skew compensation is also presented. The compensation algorithm utilises the temporal redundancy inherent in audio streams to make inaudible playout adjustments. Both algorithms have been implemented in a simulator and in a network audio application. They perform effectively over the range of observed clock rate differences and beyond

REAL TIME MICROPROCESSOR TECHNIQUES FOR A DIGITAL MULTITRACK TAPE RECORDER

Transport properties of a standard compact - cassette tape system are measured and software techniques devised to configure a low - cost,direct digital recording system. Tape - velocity variation is typically ± 10% of standard speed over tape lengths of 5 µm.with occasional variations of ±40%. Static tape - skew can result due to axial movement of the tape reel when it spools.Dynamic tape skew occurs and is primarily caused by tape - edge curvature with a constant contribution due to the transport mechanism.Spectral skew components range from 0.32 Hz to 8 Hz with magnitude normally within one 10 kbit/ sec- bit cell.The pinch roller works against the friction of the tape guides to cause tape deformation.Average values of tape deformation are 0.67 µm,0.85 µm and 1.08 µm for C60,C90 and C120 tape respectively. Parallel,software encoding / decoding algorithms have been developed for several channel codes.Adaptive software methods permit track data rates up to 3.33 k bits/sec in a rnultitrack system using a simple microcomputer.For a 4 - track system,raw error rates vary from 10ˉ⁷ at 500 bits/sec/track to 10ˉ⁵ at 3.33 kbits/sec/track.Adaptive software reduces skew - induced errors by 50%.A skew - correction technique has been developed and implemented on an 8 - track system at a track data rate of 10 k bits/sec. Real - time error correction gives a theoretical corrected error rate of 10ˉ¹¹for a raw error rate of 10ˉ⁷. Multiple track errors can cause mis - correction and interleaving is advised. Software algorithms have been devised for Reed - Solomon code. With a more powerful microprocessor this code m ay be combined with the above techniques in a layered error-correction scheme. The software techniques developed may be applied to N tracks with an N - bit computer.Recording density may be increased by using thin - film,multitrack heads and a faster computer.British Broadcasting Corporatio

Audio Cards Clock Skew Compensation over a Local Network

This paper is the continuation of a previous work done on clock skew compensation over a high latency network. It evaluates the efficiency of the EPTMA clock skew detection algorithm applied to real-time audio streaming over a local network. The presented results include real world apparent deviations of audio card clocks and acuracy of the skew detection. It appears that EPMTA is very suitable to measure clocks deviation in the context of audio transport. Finally, a simple method to compensate for the clock skew is presented, mainly to evaluate a complete solution for audio streaming

Design and Implementation Recognition System for Handwritten Hindi/Marathi Document

In the present scenario most of the importance is given for the “paperless office” there by more and more communication and storage of documents is performed digitally. Documents and files which are present in Hindi and Marathi languages that were once stored physically on paper are now being converted into electronic form in order to facilitate quicker additions, searches, and modifications, as well as to prolong the life of such records. Because of this, there is a great demand of such software, which automatically extracts, analyze, recognize and store information from physical documents for later retrieval. Skew detection is used for text line position determination in Digitized documents, automated page orientation, and skew angle detection for binary document images, skew detection in handwritten scripts, in compensation for Internet audio applications and in the correction of scanned documents

Clock Skew Compensation over a High Latency Network

International audienceExchange of time stamped events between different stations raises the problem of the clock frequencies difference as soon as one station try to compensate for the transmission delay and to render the events with a minimum time distortion. We propose a simple, efficient and low cost method to compensate for the clock frequencies difference. This method rely only on regular time stamped packets transmissions and may be used in many cases. It provides good performances to the receiver station in regard of the sender reference time even on a heavily loaded communication channel. It operates also very efficiently on a low latency local networ

Concepts for smart AD and DA converters

This thesis studies the `smart' concept for application to analog-to-digital and digital-to-analog converters. The smart concept aims at improving performance - in a wide sense - of AD/DA converters by adding on-chip intelligence to extract imperfections and to correct for them. As the smart concept can correct for certain imperfections, it can also enable the use of more efficient architectures, thus yielding an additional performance boost. Chapter 2 studies trends and expectations in converter design with respect to applications, circuit design and technology evolution. Problems and opportunities are identfied, and an overview of performance criteria is given. Chapter 3 introduces the smart concept that takes advantage of the expected opportunities (described in chapter 2) in order to solve the anticipated problems. Chapter 4 applies the smart concept to digital-to-analog converters. In the discussed example, the concept is applied to reduce the area of the analog core of a current-steering DAC. It is shown that a sub-binary variable-radix approach reduces the area of the current-source elements substantially (10x compared to state-of-the-art), while maintaining accuracy by a self-measurement and digital pre-correction scheme. Chapter 5 describes the chip implementation of the sub-binary variable-radix DAC and discusses the experimental results. The results confirm that the sub-binary variable-radix design can achieve the smallest published current-source-array area for the given accuracy (12bit). Chapter 6 applies the smart concept to analog-to-digital converters, with as main goal the improvement of the overall performance in terms of a widely used figure-of-merit. Open-loop circuitry and time interleaving are shown to be key to achieve high-speed low-power solutions. It is suggested to apply a smart approach to reduce the effect of the imperfections, unintentionally caused by these key factors. On high-level, a global picture of the smart solution is proposed that can solve the problems while still maintaining power-efficiency. Chapter 7 deals with the design of a 500MSps open-loop track-and-hold circuit. This circuit is used as a test case to demonstrate the proposed smart approaches. Experimental results are presented and compared against prior art. Though there are several limitations in the design and the measurement setup, the measured performance is comparable to existing state-of-the-art. Chapter 8 introduces the first calibration method that counteracts the accuracy issues of the open-loop track-and-hold. A description of the method is given, and the implementation of the detection algorithm and correction circuitry is discussed. The chapter concludes with experimental measurement results. Chapter 9 introduces the second calibration method that targets the accuracy issues of time-interleaved circuits, in this case a 2-channel version of the implemented track-and-hold. The detection method, processing algorithm and correction circuitry are analyzed and their implementation is explained. Experimental results verify the usefulness of the method

Clock synchronisation for UWB and DECT communication networks

Synchronisation deals with the distribution of time and/or frequency across a network of nodes dispersed in an area, in order to align their clocks with respect to time and/or frequency. It remains an important requirement in telecommunication networks, especially in Time Division Duplexing (TDD) systems such as Ultra Wideband (UWB) and Digital Enhanced Cordless Telecommunications (DECT) systems. This thesis explores three di erent research areas related to clock synchronisation in communication networks; namely algorithm development and implementation, managing Packet Delay Variation (PDV), and coping with the failure of a master node. The first area proposes a higher-layer synchronisation algorithm in order to meet the specific requirements of a UWB network that is based on the European Computer Manufacturers Association (ECMA) standard. At up to 480 Mbps data rate, UWB is an attractive technology for multimedia streaming. Higher-layer synchronisation is needed in order to facilitate synchronised playback at the receivers and prevent distortion, but no algorithm is de ned in the ECMA-368 standard. In this research area, a higher-layer synchronisation algorithm is developed for an ECMA-368 UWB network. Network simulations and FPGA implementation are used to show that the new algorithm satis es the requirements of the network. The next research area looks at how PDV can be managed when Precision Time Protocol (PTP) is implemented in an existing Ethernet network. Existing literature indicates that the performance of a PDV ltering algorithm usually depends on the delay pro le of the network in which it is applied. In this research area, a new sample-mode PDV filter is proposed which is independent of the shape of the delay profile. Numerical simulations show that the sample-mode filtering algorithm is able to match or out-perform the existing sample minimum, mean, and maximum filters, at differentlevels of network load. Finally, the thesis considers the problem of dealing with master failures in a PTP network for a DECT audio application. It describes the existing master redundancy techniques and shows why they are unsuitable for the specific application. Then a new alternate master cluster technique is proposed along with an alternative BMCA to suit the application under consideration. Network simulations are used to show how this technique leads to a reduction in the total time to recover from a master failure

CHANNEL CODING TECHNIQUES FOR A MULTIPLE TRACK DIGITAL MAGNETIC RECORDING SYSTEM

In magnetic recording greater area) bit packing densities are achieved through increasing track density by reducing space between and width of the recording tracks, and/or reducing the wavelength of the recorded information. This leads to the requirement of higher precision tape transport mechanisms and dedicated coding circuitry. A TMS320 10 digital signal processor is applied to a standard low-cost, low precision, multiple-track, compact cassette tape recording system. Advanced signal processing and coding techniques are employed to maximise recording density and to compensate for the mechanical deficiencies of this system. Parallel software encoding/decoding algorithms have been developed for several Run-Length Limited modulation codes. The results for a peak detection system show that Bi-Phase L code can be reliably employed up to a data rate of 5kbits/second/track. Development of a second system employing a TMS32025 and sampling detection permitted the utilisation of adaptive equalisation to slim the readback pulse. Application of conventional read equalisation techniques, that oppose inter-symbol interference, resulted in a 30% increase in performance. Further investigation shows that greater linear recording densities can be achieved by employing Partial Response signalling and Maximum Likelihood Detection. Partial response signalling schemes use controlled inter-symbol interference to increase recording density at the expense of a multi-level read back waveform which results in an increased noise penalty. Maximum Likelihood Sequence detection employs soft decisions on the readback waveform to recover this loss. The associated modulation coding techniques required for optimised operation of such a system are discussed. Two-dimensional run-length-limited (d, ky) modulation codes provide a further means of increasing storage capacity in multi-track recording systems. For example the code rate of a single track run length-limited code with constraints (1, 3), such as Miller code, can be increased by over 25% when using a 4-track two-dimensional code with the same d constraint and with the k constraint satisfied across a number of parallel channels. The k constraint along an individual track, kx, can be increased without loss of clock synchronisation since the clocking information derived by frequent signal transitions can be sub-divided across a number of, y, parallel tracks in terms of a ky constraint. This permits more code words to be generated for a given (d, k) constraint in two dimensions than is possible in one dimension. This coding technique is furthered by development of a reverse enumeration scheme based on the trellis description of the (d, ky) constraints. The application of a two-dimensional code to a high linear density system employing extended class IV partial response signalling and maximum likelihood detection is proposed. Finally, additional coding constraints to improve spectral response and error performance are discussed.Hewlett Packard, Computer Peripherals Division (Bristol