Metodologia Per la Caratterizzazione di amplificatori a basso rumore per UMTS

In questo lavoro si presenta una metodologia di progettazione elettronica a livello di sistema, affrontando il problema della caratterizzazione dello spazio di progetto dell' amplificatore a basso rumore costituente il primo stadio di un front end a conversione diretta per UMTS realizzato in tecnologia CMOS con lunghezza di canale .18u. La metodologia è sviluppata al fine di valutare in modo quantititativo le specifiche ottime di sistema per il front-end stesso e si basa sul concetto di Piattaforma Analogica, che prevede la costruzione di un modello di prestazioni per il blocco analogico basato su campionamento statistico di indici di prestazioni del blocco stesso, misurati tramite simulazione di dimensionamenti dei componenti attivi e passivi soddisfacenti un set di equazioni specifico della topologia circuitale. Gli indici di prestazioni vengono successivamente ulizzati per parametrizzare modelli comportamentali utilizzati nelle fasi di ottimizzazione a livello di sistema. Modelli comportamentali atti a rappresentare i sistemi RF sono stati pertanto studiati per ottimizzare la scelta delle metriche di prestazioni. L'ottimizzazione dei set di equazioni atti a selezionare le configurazione di interesse per il campionamento ha al tempo stesso richiesto l'approfondimento dei modelli di dispositivi attivi validi in tutte le regioni di funzionamento, e lo studio dettagliato della progettazione degli amplificatori a basso rumore basati su degenerazione induttiva. Inoltre, il problema della modellizzazione a livello di sistema degli effetti della comunicazione tra LNA e Mixer è stato affrontato proponendo e analizzando diverse soluzioni. Il lavoro ha permesso di condurre un'ottimizzazione del front-end UMTS, giungendo a specifiche ottime a livello di sistema per l'amplificatore stesso

Load-mismatch sensitivity of class-E power amplifiers

Class-E RF power amplifiers (PAs) are very power efficient under nominal operating conditions. Due to incorporating two tuned tanks, the dependence on the load impedance is, however, relatively large, resulting in, e.g., load-dependent output power, power efficiency, peak voltages, and peak (and average) currents which can lead to reliability issues. This paper presents load-pull analyses for class-E RF PAs from a mathematical perspective, with analyses and discussions of the effects of the most common nonidealities of class-E PAs: the limited loaded quality factor (Qloaded) of the series filter, switch on-resistance, the limited quality factor of the dc-feed inductor, load mismatch-dependent switch conduction loss, and the limited negative voltage excursions (due to, e.g., the reverse conduction of the switch transistor for negative voltage excursions). The theoretical findings are backed up by extensive circuit simulations and load-pull measurements of a class-E PA implemented in 65-nm CMOS technology. The PA provides 18.1-dBm output power and 72% efficiency at 1.4 GHz under nominal operating condition employing an off-chip matching network

Vidutinių dažnių 5G belaidžių tinklų galios stiprintuvų tyrimas

This dissertation addresses the problems of ensuring efficient radio fre-quency transmission for 5G wireless networks. Taking into account, that the next generation 5G wireless network structure will be heterogeneous, the device density and their mobility will increase and massive MIMO connectivity capability will be widespread, the main investigated problem is formulated – increasing the efficiency of portable mid-band 5G wireless network CMOS power amplifier with impedance matching networks. The dissertation consists of four parts including the introduction, 3 chapters, conclusions, references and 3 annexes. The investigated problem, importance and purpose of the thesis, the ob-ject of the research methodology, as well as the scientific novelty are de-fined in the introduction. Practical significance of the obtained results, defended state-ments and the structure of the dissertation are also included. The first chapter presents an extensive literature analysis. Latest ad-vances in the structure of the modern wireless network and the importance of the power amplifier in the radio frequency transmission chain are de-scribed in detail. The latter is followed by different power amplifier archi-tectures, parameters and their improvement techniques. Reported imped-ance matching network design methods are also discussed. Chapter 1 is concluded distinguishing the possible research vectors and defining the problems raised in this dissertation. The second chapter is focused around improving the accuracy of de-signing lumped impedance matching network. The proposed methodology of estimating lumped inductor and capacitor parasitic parameters is dis-cussed in detail provi-ding complete mathematical expressions, including a summary and conclusions. The third chapter presents simulation results for the designed radio fre-quency power amplifiers. Two variations of Doherty power amplifier archi-tectures are presented in the second part, covering the full step-by-step de-sign and simulation process. The latter chapter is concluded by comparing simulation and measurement results for all designed radio frequency power amplifiers. General conclusions are followed by an extensive list of references and a list of 5 publications by the author on the topic of the dissertation. 5 papers, focusing on the subject of the discussed dissertation, have been published: three papers are included in the Clarivate Analytics Web of Sci-ence database with a citation index, one paper is included in Clarivate Ana-lytics Web of Science database Conference Proceedings, and one paper has been published in unreferred international conference preceedings. The au-thor has also made 9 presentations at 9 scientific conferences at a national and international level.Dissertatio

A Precise analysis of a class e amplifier

An analytical approach to the design and simulation of a Class-E power amplifier under typical high frequency switching conditions is presented. The analysis will optimize the loading network at the output for transistors with an exponential transition current, while accounting for harmonics injected into the circuit from the choke inductor and a non-infinite output Q. Two methods have been successfully implemented to simulate the class-E amplifier waveforms, optimize the required circuit components, and calculate amplifier performances such as efficiency and total harmonic distortion (THD). The first optimizes the circuit parameters while considering finite choke inductances, drain current fall time, and loaded quality factor of the output network inductance. The second accounts for all these in addition to a finite ON resistance of the switch, rise and fall time of the input signal, and parasitic resistances of both circuit inductors. The first method (integral method) utilizes an iterative technique where each waveform is defined symbolically and solved using the integral function in MATLAB. Initial values are assumed and an iterative process is implemented to quickly arrive at the desired results. The second method (finite difference method) expresses the circuit equations using differential equations and solves them simultaneously using finite difference technique. The results of the theoretical analysis is then compared to a commercial circuit simulation software program (Spectre ©) as well as to a low frequency hardware circuit utilizing discrete components. The presented analysis is shown to accurately model the high frequency simulation as well as the actual hardware circuit with the results discussed

CMOS analog-digital circuit components for low power applications

Dissertação de mestrado em Micro and NanoelectronicsThis dissertation presents a study in the area of mixed analog/digital CMOS power extraction circuits for energy harvester. The main contribution of this work is the realization of low power consumption and high efficient circuit components employable in a management circuit for piezoelectricbased energy harvester. This thesis focuses on the development of current references and operational amplifiers addressing low power demands. A brief literature review is conducted on the components necessary for the power extraction circuit, including introduction to CMOS technology design and research of known low power circuits. It is presented with multiple implementations for voltage and current references, as well for operational amplifier designs. A self-biased current reference, capable of driving the remaining harvesting circuit, is designed and verified. A novel operational amplifier is proposed by the use of a minimum current selector circuit topology. It is a three-stage amplifier with an AB class output stage, comprised by a translinear circuit. The circuit is designed, taking into consideration noise reduction. The circuit components are designed based on the 0.35mm CMOS technology. A physical layout is developed for fabrication purposes. This technology was chosen with consideration of robustness, costliness and performance. The current reference is capable of outputting a stable 12nA current, which may remain stable in a broad range of power supply voltages with a minimum voltage of 1.6V. The operational amplifier operates correctly at voltages as low as 1.5V. The amplifier power consumption is extremely low, around 8mW, with an optimal quiescent current and minimum current preservation in the output stage.A principal contribuição desta dissertação é a implementação de circuitos integrados de muito baixo consumo e alta eficiência, prontos a ser implementados num circuito de extração de energia com base num elemento piezoelétrico. Esta tese foca-se no desenvolvimento de um circuito de referência de corrente e um amplificador operacional com baixa exigência de consumo. Uma revisão da literatura é realizada, incluindo introdução à tecnologia Complementary Metal-Oxide-Semiconductor (CMOS), e implementação de conhecidos circuitos de baixo consumo. Várias implementações de referência de tensão e corrente são consideradas, e amplificadores operacionais também. Uma referência de corrente auto polarizada com extremo baixo consumo é desenvolvida e verificada. Um amplificador operacional original é proposto com uma topologia de seleção de corrente mínima. Este circuito é constituído por três estágios, com um estágio de saída de classe AB, e um circuito translinear. O circuito tem em consideração redução de ruído na sua implementação. Os circuitos são desenvolvidos com base na tecnologia 0.35mm CMOS. Uma layout foi também desenhada com o propósito de fabricação. A tecnologia foi escolhida tendo em conta o seu custo versus desempenho. A referência de corrente produz uma corrente de 12nA, permanecendo estável para tensões de alimentação de variáveis, com uma tensão mínima de 1.6V. O circuito mostra um coeficiente de temperatura satisfatório. O amplificador operacional funciona com tensão de alimentação mínima de 1.5V, com um consumo baixo de 8mW, com uma corrente mínima mantida no estágio de saída

An Analytical Approach for Memristive Nanoarchitectures

As conventional memory technologies are challenged by their technological physical limits, emerging technologies driven by novel materials are becoming an attractive option for future memory architectures. Among these technologies, Resistive Memories (ReRAM) created new possibilities because of their nano-features and unique $I$-$V$ characteristics. One particular problem that limits the maximum array size is interference from neighboring cells due to sneak-path currents. A possible device level solution to address this issue is to implement a memory array using complementary resistive switches (CRS). Although the storage mechanism for a CRS is fundamentally different from what has been reported for memristors (low and high resistances), a CRS is simply formed by two series bipolar memristors with opposing polarities. In this paper our intention is to introduce modeling principles that have been previously verified through measurements and extend the simulation principles based on memristors to CRS devices and hence provide an analytical approach to the design of a CRS array. The presented approach creates the necessary design methodology platform that will assist designers in implementation of CRS devices in future systems.Comment: 12 pages, 10 figures, 4 table