2,784 research outputs found

    Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding

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    Real-time and high-quality video coding is gaining a wide interest in the research and industrial community for different applications. H.264/AVC, a recent standard for high performance video coding, can be successfully exploited in several scenarios including digital video broadcasting, high-definition TV and DVD-based systems, which require to sustain up to tens of Mbits/s. To that purpose this paper proposes optimized architectures for H.264/AVC most critical tasks, Motion estimation and context adaptive binary arithmetic coding. Post synthesis results on sub-micron CMOS standard-cells technologies show that the proposed architectures can actually process in real-time 720 × 480 video sequences at 30 frames/s and grant more than 50 Mbits/s. The achieved circuit complexity and power consumption budgets are suitable for their integration in complex VLSI multimedia systems based either on AHB bus centric on-chip communication system or on novel Network-on-Chip (NoC) infrastructures for MPSoC (Multi-Processor System on Chip

    A Scalable VLSI Architecture for Soft-Input Soft-Output Depth-First Sphere Decoding

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    Multiple-input multiple-output (MIMO) wireless transmission imposes huge challenges on the design of efficient hardware architectures for iterative receivers. A major challenge is soft-input soft-output (SISO) MIMO demapping, often approached by sphere decoding (SD). In this paper, we introduce the - to our best knowledge - first VLSI architecture for SISO SD applying a single tree-search approach. Compared with a soft-output-only base architecture similar to the one proposed by Studer et al. in IEEE J-SAC 2008, the architectural modifications for soft input still allow a one-node-per-cycle execution. For a 4x4 16-QAM system, the area increases by 57% and the operating frequency degrades by 34% only.Comment: Accepted for IEEE Transactions on Circuits and Systems II Express Briefs, May 2010. This draft from April 2010 will not be updated any more. Please refer to IEEE Xplore for the final version. *) The final publication will appear with the modified title "A Scalable VLSI Architecture for Soft-Input Soft-Output Single Tree-Search Sphere Decoding

    Recent advances in coding theory for near error-free communications

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    Channel and source coding theories are discussed. The following subject areas are covered: large constraint length convolutional codes (the Galileo code); decoder design (the big Viterbi decoder); Voyager's and Galileo's data compression scheme; current research in data compression for images; neural networks for soft decoding; neural networks for source decoding; finite-state codes; and fractals for data compression

    Modulation and coding technology for deep space and satellite applications

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    Modulation and coding research and development at the Jet Propulsion Laboratory (JPL) currently emphasize Deep Space Communications Systems and advanced near earth Commercial Satellite Communications Systems. The Deep Space Communication channel is extremely signal to noise ratio limited and has long transmission delay. The near earth satellite channel is bandwidth limited with fading and multipath. Recent code search efforts at JPL have found a long constraint, low rate convolutional code (15, 1/6) which, when concatenated with a ten bit Reed-Solomon (RS) code, provides a 2.1 dB gain over that of the Voyager spacecraft - the current standard. The new code is only 2 dB from the theoretical Shannon limit. A flight qualified version of the (15, 1/6) convolutional encoder was implemented on the Galileo Spacecraft to be launched later this year. An L-band mobile link, use of the Ka-band for personal communications, and the development of subsystem technology for the interconnection of satellite resources by using high rate optical inter-satellite links are noted
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